Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	339754	1		T1	2		T2	2		T3	1
all_values[1]	339754	1		T1	2		T2	2		T3	1
all_values[2]	339754	1		T1	2		T2	2		T3	1
all_values[3]	339754	1		T1	2		T2	2		T3	1
all_values[4]	339754	1		T1	2		T2	2		T3	1
all_values[5]	339754	1		T1	2		T2	2		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	685891	1		T1	12		T2	12		T3	6
auto[1]	1352633	1		T4	24080		T6	12776		T30	5448

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	991454	1		T1	7		T2	7		T3	4
auto[1]	1047070	1		T1	5		T2	5		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	339589	1		T1	2		T2	2		T3	1
all_values[0]	auto[1]	auto[1]	165	1		T257	5		T326	3		T328	1
all_values[1]	auto[0]	auto[1]	339586	1		T1	2		T2	2		T3	1
all_values[1]	auto[1]	auto[1]	168	1		T257	7		T258	2		T326	7
all_values[2]	auto[0]	auto[0]	1606	1		T1	2		T2	2		T3	1
all_values[2]	auto[0]	auto[1]	64	1		T257	2		T258	1		T326	2
all_values[2]	auto[1]	auto[0]	338024	1		T4	6020		T6	3194		T30	1362
all_values[2]	auto[1]	auto[1]	60	1		T258	1		T326	2		T328	3
all_values[3]	auto[0]	auto[0]	1624	1		T1	2		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	74	1		T257	2		T258	1		T326	2
all_values[3]	auto[1]	auto[0]	69393	1		T6	1597		T30	681		T124	1616
all_values[3]	auto[1]	auto[1]	268663	1		T4	6020		T6	1597		T30	681
all_values[4]	auto[0]	auto[0]	1143	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	524	1		T1	1		T2	1		T5	1
all_values[4]	auto[1]	auto[0]	240091	1		T4	4515		T6	1597		T30	681
all_values[4]	auto[1]	auto[1]	97996	1		T4	1505		T6	1597		T30	681
all_values[5]	auto[0]	auto[0]	1572	1		T1	2		T2	2		T3	1
all_values[5]	auto[0]	auto[1]	109	1		T5	1		T35	1		T36	1
all_values[5]	auto[1]	auto[0]	338001	1		T4	6020		T6	3194		T30	1362
all_values[5]	auto[1]	auto[1]	72	1		T257	4		T258	1		T326	1