Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	2	14	87.50

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	2	14	87.50	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	249140	1		T1	2		T2	1684		T3	4
auto[FlashEraseBank]	279512	1		T2	1890		T3	9		T4	638

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	263690	1		T2	1271		T3	12		T4	1505
auto[FlashOpProgram]	245718	1		T1	1		T2	2303		T3	1
auto[FlashOpErase]	15244	1		T1	1		T10	8		T21	57
auto[FlashOpInvalid]	4000	1		T132	200		T215	200		T140	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	263690	1		T2	1271		T3	12		T4	1505
op[FlashOpProgram]	245718	1		T1	1		T2	2303		T3	1
op[FlashOpErase]	15244	1		T1	1		T10	8		T21	57
read_erase_read	537	1		T10	2		T21	8		T22	1
read_prog_read	887	1		T2	6		T3	1		T10	2

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	390717	1		T2	2985		T3	2		T4	1505
auto[FlashPartInfo]	134315	1		T1	2		T2	572		T3	10
auto[FlashPartInfo1]	820	1		T2	1		T30	24		T5	4
auto[FlashPartInfo2]	2800	1		T2	16		T3	1		T30	19

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	2	14	87.50	2

Automatically Generated Cross Bins for op_part_cross

Uncovered bins

part_cp	op_cp	COUNT	AT LEAST	NUMBER
[auto[FlashPartInfo1]]	[auto[FlashOpErase] , auto[FlashOpInvalid]]	--	--	2

Covered bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	194293	1		T2	920		T3	1		T4	1505
auto[FlashPartData]	auto[FlashOpProgram]	188869	1		T2	2065		T3	1		T10	30
auto[FlashPartData]	auto[FlashOpErase]	3629	1		T10	8		T21	37		T22	5
auto[FlashPartData]	auto[FlashOpInvalid]	3926	1		T132	194		T215	200		T140	194
auto[FlashPartInfo]	auto[FlashOpRead]	66931	1		T2	343		T3	10		T10	1
auto[FlashPartInfo]	auto[FlashOpProgram]	55734	1		T1	1		T2	229		T5	12
auto[FlashPartInfo]	auto[FlashOpErase]	11588	1		T1	1		T21	20		T57	143
auto[FlashPartInfo]	auto[FlashOpInvalid]	62	1		T132	6		T140	4		T346	4
auto[FlashPartInfo1]	auto[FlashOpRead]	655	1		T2	1		T30	24		T5	4
auto[FlashPartInfo1]	auto[FlashOpProgram]	165	1		T21	1		T64	32		T65	32
auto[FlashPartInfo2]	auto[FlashOpRead]	1811	1		T2	7		T3	1		T30	19
auto[FlashPartInfo2]	auto[FlashOpProgram]	950	1		T2	9		T5	1		T114	11
auto[FlashPartInfo2]	auto[FlashOpErase]	27	1		T115	1		T133	1		T128	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	12	1		T140	2		T347	2		T348	2