Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29935	1		T10	4		T21	36		T57	280
auto[1]	48	1		T74	4		T288	1		T76	4
auto[2]	68	1		T113	4		T184	3		T390	1
auto[3]	184	1		T3	1		T26	1		T125	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7562	1		T3	1		T10	1		T21	9
evic_idx[1]	7557	1		T10	1		T21	9		T57	70
evic_idx[2]	7557	1		T10	1		T21	9		T57	70
evic_idx[3]	7559	1		T10	1		T21	9		T57	70

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	29342	1		T57	280		T41	268		T89	336
evic_op[2]	336	1		T3	1		T26	1		T125	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7283	1		T57	70		T41	67		T89	84
evic_idx[0]	evic_op[1]	auto[1]	10	1		T74	1		T391	3		T213	3
evic_idx[0]	evic_op[1]	auto[2]	9	1		T213	1		T392	6		T153	1
evic_idx[0]	evic_op[1]	auto[3]	35	1		T74	3		T184	2		T393	3
evic_idx[0]	evic_op[2]	auto[0]	67	1		T143	1		T244	1		T394	10
evic_idx[0]	evic_op[2]	auto[1]	4	1		T76	1		T321	1		T214	1
evic_idx[0]	evic_op[2]	auto[2]	4	1		T113	1		T214	1		T395	1
evic_idx[0]	evic_op[2]	auto[3]	10	1		T3	1		T34	1		T396	1
evic_idx[1]	evic_op[1]	auto[0]	7281	1		T57	70		T41	67		T89	84
evic_idx[1]	evic_op[1]	auto[1]	7	1		T74	1		T391	3		T213	2
evic_idx[1]	evic_op[1]	auto[2]	10	1		T390	1		T213	2		T392	5
evic_idx[1]	evic_op[1]	auto[3]	35	1		T74	5		T184	1		T393	3
evic_idx[1]	evic_op[2]	auto[0]	69	1		T186	1		T244	1		T394	10
evic_idx[1]	evic_op[2]	auto[1]	4	1		T76	1		T397	1		T395	1
evic_idx[1]	evic_op[2]	auto[2]	2	1		T113	1		T398	1		-	-
evic_idx[1]	evic_op[2]	auto[3]	9	1		T26	1		T125	1		T399	1
evic_idx[2]	evic_op[1]	auto[0]	7282	1		T57	70		T41	67		T89	84
evic_idx[2]	evic_op[1]	auto[1]	5	1		T74	1		T391	3		T392	1
evic_idx[2]	evic_op[1]	auto[2]	9	1		T184	1		T400	2		T392	4
evic_idx[2]	evic_op[1]	auto[3]	36	1		T74	2		T184	1		T393	3
evic_idx[2]	evic_op[2]	auto[0]	67	1		T244	1		T324	1		T394	10
evic_idx[2]	evic_op[2]	auto[1]	4	1		T76	1		T321	1		T281	1
evic_idx[2]	evic_op[2]	auto[2]	4	1		T113	1		T214	1		T395	1
evic_idx[2]	evic_op[2]	auto[3]	11	1		T286	1		T401	1		T402	1
evic_idx[3]	evic_op[1]	auto[0]	7284	1		T57	70		T41	67		T89	84
evic_idx[3]	evic_op[1]	auto[1]	9	1		T74	1		T391	4		T213	2
evic_idx[3]	evic_op[1]	auto[2]	7	1		T184	2		T400	1		T392	2
evic_idx[3]	evic_op[1]	auto[3]	40	1		T74	1		T184	1		T393	5
evic_idx[3]	evic_op[2]	auto[0]	65	1		T244	1		T394	10		T116	2
evic_idx[3]	evic_op[2]	auto[1]	5	1		T288	1		T76	1		T403	1
evic_idx[3]	evic_op[2]	auto[2]	3	1		T113	1		T214	1		T404	1
evic_idx[3]	evic_op[2]	auto[3]	8	1		T97	1		T218	1		T186	1