Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	33540	1		T332	1209		T333	2146		T334	13999
rd_lvl[2]	44342	1		T332	2264		T335	2391		T333	1214
rd_lvl[3]	15545	1		T46	1275		T332	533		T335	1990
rd_lvl[4]	46952	1		T4	5114		T46	5790		T106	5611
rd_lvl[5]	15933	1		T4	906		T46	1005		T229	866
rd_lvl[6]	15707	1		T229	215		T336	2460		T332	1316
rd_lvl[7]	9097	1		T206	1041		T337	1909		T338	548
rd_lvl[8]	18249	1		T229	98		T206	778		T279	3141
rd_lvl[9]	4269	1		T206	30		T279	451		T109	17
rd_lvl[10]	6259	1		T30	517		T287	1190		T339	71
rd_lvl[11]	6247	1		T30	163		T229	98		T287	528
rd_lvl[12]	5826	1		T124	1287		T340	333		T341	148
rd_lvl[13]	3127	1		T30	1		T124	329		T340	174
rd_lvl[14]	4458	1		T341	59		T342	1214		T333	53
rd_lvl[15]	2708	1		T6	525		T33	514		T340	6