Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	339754	1		T1	2		T2	2		T3	1
all_pins[1]	339754	1		T1	2		T2	2		T3	1
all_pins[2]	339754	1		T1	2		T2	2		T3	1
all_pins[3]	339754	1		T1	2		T2	2		T3	1
all_pins[4]	339754	1		T1	2		T2	2		T3	1
all_pins[5]	339754	1		T1	2		T2	2		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1695539	1		T1	12		T2	12		T3	6
values[0x1]	342985	1		T4	7525		T6	5276		T30	1362
transitions[0x0=>0x1]	305038	1		T4	6020		T6	3194		T30	1362
transitions[0x1=>0x0]	305017	1		T4	6020		T6	3194		T30	1362

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	339589	1		T1	2		T2	2		T3	1
all_pins[0]	values[0x1]	165	1		T257	5		T326	3		T328	1
all_pins[0]	transitions[0x0=>0x1]	87	1		T326	1		T328	1		T327	5
all_pins[0]	transitions[0x1=>0x0]	90	1		T257	2		T258	2		T326	5
all_pins[1]	values[0x0]	339586	1		T1	2		T2	2		T3	1
all_pins[1]	values[0x1]	168	1		T257	7		T258	2		T326	7
all_pins[1]	transitions[0x0=>0x1]	139	1		T257	7		T258	2		T326	5
all_pins[1]	transitions[0x1=>0x0]	2741	1		T6	1041		T33	963		T349	147
all_pins[2]	values[0x0]	336984	1		T1	2		T2	2		T3	1
all_pins[2]	values[0x1]	2770	1		T6	1041		T33	963		T349	147
all_pins[2]	transitions[0x0=>0x1]	46	1		T326	2		T328	1		T327	2
all_pins[2]	transitions[0x1=>0x0]	232400	1		T4	6020		T6	556		T30	681
all_pins[3]	values[0x0]	104630	1		T1	2		T2	2		T3	1
all_pins[3]	values[0x1]	235124	1		T4	6020		T6	1597		T30	681
all_pins[3]	transitions[0x0=>0x1]	200072	1		T4	4515		T6	556		T30	681
all_pins[3]	transitions[0x1=>0x0]	69634	1		T6	1597		T30	681		T124	1616
all_pins[4]	values[0x0]	235068	1		T1	2		T2	2		T3	1
all_pins[4]	values[0x1]	104686	1		T4	1505		T6	2638		T30	681
all_pins[4]	transitions[0x0=>0x1]	104660	1		T4	1505		T6	2638		T30	681
all_pins[4]	transitions[0x1=>0x0]	46	1		T257	4		T258	1		T326	1
all_pins[5]	values[0x0]	339682	1		T1	2		T2	2		T3	1
all_pins[5]	values[0x1]	72	1		T257	4		T258	1		T326	1
all_pins[5]	transitions[0x0=>0x1]	34	1		T257	2		T258	1		T328	3
all_pins[5]	transitions[0x1=>0x0]	106	1		T257	2		T326	2		T327	3