Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
83.33 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 36 8 28 77.78


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 6 0 6 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 36 8 28 77.78 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 293 1 T257 7 T258 4 T326 7
all_values[1] 293 1 T257 7 T258 4 T326 7
all_values[2] 293 1 T257 7 T258 4 T326 7
all_values[3] 293 1 T257 7 T258 4 T326 7
all_values[4] 293 1 T257 7 T258 4 T326 7
all_values[5] 293 1 T257 7 T258 4 T326 7



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 949 1 T257 19 T258 14 T326 24
auto[1] 809 1 T257 23 T258 10 T326 18



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 563 1 T257 15 T258 7 T326 11
auto[1] 1195 1 T257 27 T258 17 T326 31



Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1030 1 T257 27 T258 12 T326 22
auto[1] 728 1 T257 15 T258 12 T326 20



Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 36 8 28 77.78 8
Automatically Generated Cross Bins 36 8 28 77.78 8
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBER
[all_values[0] , all_values[1]] [auto[0]] * [auto[0]] -- -- 4
[all_values[2] , all_values[3]] [auto[0]] * [auto[1]] -- -- 4


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[1] 91 1 T257 3 T258 1 T326 4
all_values[0] auto[0] auto[1] auto[1] 83 1 T257 2 T326 1 T327 2
all_values[0] auto[1] auto[0] auto[1] 65 1 T257 2 T258 3 T328 1
all_values[0] auto[1] auto[1] auto[1] 54 1 T326 2 T328 2 T327 1
all_values[1] auto[0] auto[0] auto[1] 86 1 T258 1 T328 2 T327 4
all_values[1] auto[0] auto[1] auto[1] 87 1 T257 4 T258 1 T326 4
all_values[1] auto[1] auto[0] auto[1] 62 1 T257 2 T326 1 T328 2
all_values[1] auto[1] auto[1] auto[1] 58 1 T257 1 T258 2 T326 2
all_values[2] auto[0] auto[0] auto[0] 90 1 T257 3 T258 1 T326 1
all_values[2] auto[0] auto[1] auto[0] 79 1 T257 2 T258 1 T326 2
all_values[2] auto[1] auto[0] auto[1] 73 1 T257 2 T258 2 T326 3
all_values[2] auto[1] auto[1] auto[1] 51 1 T326 1 T328 1 T327 2
all_values[3] auto[0] auto[0] auto[0] 101 1 T257 1 T326 3 T328 2
all_values[3] auto[0] auto[1] auto[0] 62 1 T257 3 T258 2 T328 1
all_values[3] auto[1] auto[0] auto[1] 75 1 T257 1 T258 2 T326 2
all_values[3] auto[1] auto[1] auto[1] 55 1 T257 2 T326 2 T328 2
all_values[4] auto[0] auto[0] auto[0] 54 1 T257 1 T258 1 T326 1
all_values[4] auto[0] auto[0] auto[1] 25 1 T327 1 T329 2 T330 1
all_values[4] auto[0] auto[1] auto[0] 65 1 T257 4 T326 1 T328 2
all_values[4] auto[0] auto[1] auto[1] 24 1 T257 1 T258 1 T328 1
all_values[4] auto[1] auto[0] auto[1] 68 1 T258 2 T326 4 T328 1
all_values[4] auto[1] auto[1] auto[1] 57 1 T257 1 T326 1 T328 3
all_values[5] auto[0] auto[0] auto[0] 64 1 T257 1 T258 1 T326 2
all_values[5] auto[0] auto[0] auto[1] 31 1 T326 2 T329 1 T331 2
all_values[5] auto[0] auto[1] auto[0] 48 1 T258 1 T326 1 T327 1
all_values[5] auto[0] auto[1] auto[1] 40 1 T257 2 T258 1 T328 2
all_values[5] auto[1] auto[0] auto[1] 64 1 T257 3 T326 1 T328 1
all_values[5] auto[1] auto[1] auto[1] 46 1 T257 1 T258 1 T326 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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