| T1074 |
/workspace/coverage/default/18.flash_ctrl_intr_rd.1018237870 |
|
|
Jul 07 06:17:47 PM PDT 24 |
Jul 07 06:21:45 PM PDT 24 |
1623751300 ps |
| T1075 |
/workspace/coverage/default/25.flash_ctrl_hw_sec_otp.600781702 |
|
|
Jul 07 06:18:21 PM PDT 24 |
Jul 07 06:19:52 PM PDT 24 |
3999794800 ps |
| T1076 |
/workspace/coverage/default/9.flash_ctrl_otp_reset.759151439 |
|
|
Jul 07 06:16:05 PM PDT 24 |
Jul 07 06:17:56 PM PDT 24 |
41179200 ps |
| T1077 |
/workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.3010479006 |
|
|
Jul 07 06:18:10 PM PDT 24 |
Jul 07 06:22:27 PM PDT 24 |
12574477000 ps |
| T1078 |
/workspace/coverage/default/5.flash_ctrl_otp_reset.3577404396 |
|
|
Jul 07 06:14:56 PM PDT 24 |
Jul 07 06:17:07 PM PDT 24 |
39375900 ps |
| T1079 |
/workspace/coverage/default/5.flash_ctrl_hw_sec_otp.2015394961 |
|
|
Jul 07 06:15:03 PM PDT 24 |
Jul 07 06:17:06 PM PDT 24 |
10941322600 ps |
| T1080 |
/workspace/coverage/default/9.flash_ctrl_rw.4085998056 |
|
|
Jul 07 06:15:52 PM PDT 24 |
Jul 07 06:24:06 PM PDT 24 |
3618775400 ps |
| T1081 |
/workspace/coverage/default/3.flash_ctrl_read_word_sweep_derr.73355324 |
|
|
Jul 07 06:14:32 PM PDT 24 |
Jul 07 06:14:54 PM PDT 24 |
33531900 ps |
| T1082 |
/workspace/coverage/default/1.flash_ctrl_error_prog_type.2146032273 |
|
|
Jul 07 06:14:04 PM PDT 24 |
Jul 07 06:54:32 PM PDT 24 |
2169153100 ps |
| T1083 |
/workspace/coverage/default/14.flash_ctrl_rw_evict.1667443708 |
|
|
Jul 07 06:16:56 PM PDT 24 |
Jul 07 06:17:28 PM PDT 24 |
30709500 ps |
| T1084 |
/workspace/coverage/default/0.flash_ctrl_read_word_sweep_derr.3482683688 |
|
|
Jul 07 06:14:02 PM PDT 24 |
Jul 07 06:14:26 PM PDT 24 |
34720200 ps |
| T1085 |
/workspace/coverage/default/60.flash_ctrl_otp_reset.1424822766 |
|
|
Jul 07 06:20:01 PM PDT 24 |
Jul 07 06:22:15 PM PDT 24 |
42570600 ps |
| T1086 |
/workspace/coverage/default/3.flash_ctrl_intr_wr.19255472 |
|
|
Jul 07 06:14:32 PM PDT 24 |
Jul 07 06:15:42 PM PDT 24 |
10269091700 ps |
| T1087 |
/workspace/coverage/default/9.flash_ctrl_rw_evict.4293983563 |
|
|
Jul 07 06:15:56 PM PDT 24 |
Jul 07 06:16:25 PM PDT 24 |
66604100 ps |
| T1088 |
/workspace/coverage/default/43.flash_ctrl_otp_reset.1511869937 |
|
|
Jul 07 06:19:36 PM PDT 24 |
Jul 07 06:21:27 PM PDT 24 |
40920900 ps |
| T1089 |
/workspace/coverage/default/37.flash_ctrl_intr_rd_slow_flash.3225490532 |
|
|
Jul 07 06:19:21 PM PDT 24 |
Jul 07 06:21:47 PM PDT 24 |
12752495000 ps |
| T1090 |
/workspace/coverage/default/1.flash_ctrl_lcmgr_intg.2491540485 |
|
|
Jul 07 06:14:11 PM PDT 24 |
Jul 07 06:14:25 PM PDT 24 |
16030900 ps |
| T1091 |
/workspace/coverage/default/13.flash_ctrl_hw_sec_otp.3710294319 |
|
|
Jul 07 06:16:45 PM PDT 24 |
Jul 07 06:19:01 PM PDT 24 |
8923204500 ps |
| T1092 |
/workspace/coverage/default/26.flash_ctrl_connect.3904857582 |
|
|
Jul 07 06:18:31 PM PDT 24 |
Jul 07 06:18:47 PM PDT 24 |
27502200 ps |
| T1093 |
/workspace/coverage/default/42.flash_ctrl_disable.3085635188 |
|
|
Jul 07 06:19:34 PM PDT 24 |
Jul 07 06:19:57 PM PDT 24 |
30512600 ps |
| T1094 |
/workspace/coverage/default/48.flash_ctrl_alert_test.268398954 |
|
|
Jul 07 06:19:53 PM PDT 24 |
Jul 07 06:20:07 PM PDT 24 |
44591000 ps |
| T1095 |
/workspace/coverage/default/49.flash_ctrl_smoke.1148046434 |
|
|
Jul 07 06:19:53 PM PDT 24 |
Jul 07 06:20:43 PM PDT 24 |
18786500 ps |
| T1096 |
/workspace/coverage/default/0.flash_ctrl_phy_arb.601814194 |
|
|
Jul 07 06:13:55 PM PDT 24 |
Jul 07 06:17:00 PM PDT 24 |
45972800 ps |
| T105 |
/workspace/coverage/default/0.flash_ctrl_sec_cm.370267816 |
|
|
Jul 07 06:14:03 PM PDT 24 |
Jul 07 07:35:03 PM PDT 24 |
6569048800 ps |
| T1097 |
/workspace/coverage/default/16.flash_ctrl_lcmgr_intg.2856170403 |
|
|
Jul 07 06:17:20 PM PDT 24 |
Jul 07 06:17:35 PM PDT 24 |
15836700 ps |
| T1098 |
/workspace/coverage/default/22.flash_ctrl_rw_evict_all_en.192355093 |
|
|
Jul 07 06:18:13 PM PDT 24 |
Jul 07 06:18:44 PM PDT 24 |
30093900 ps |
| T1099 |
/workspace/coverage/default/36.flash_ctrl_connect.2356825253 |
|
|
Jul 07 06:19:16 PM PDT 24 |
Jul 07 06:19:30 PM PDT 24 |
28211600 ps |
| T1100 |
/workspace/coverage/default/16.flash_ctrl_otp_reset.732760175 |
|
|
Jul 07 06:17:18 PM PDT 24 |
Jul 07 06:19:31 PM PDT 24 |
185557700 ps |
| T1101 |
/workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.606998663 |
|
|
Jul 07 06:16:52 PM PDT 24 |
Jul 07 06:19:17 PM PDT 24 |
6117181700 ps |
| T1102 |
/workspace/coverage/default/10.flash_ctrl_phy_arb.1672268313 |
|
|
Jul 07 06:16:06 PM PDT 24 |
Jul 07 06:17:11 PM PDT 24 |
43701400 ps |
| T1103 |
/workspace/coverage/default/7.flash_ctrl_rw_evict_all_en.1715902315 |
|
|
Jul 07 06:15:29 PM PDT 24 |
Jul 07 06:15:59 PM PDT 24 |
299597000 ps |
| T1104 |
/workspace/coverage/default/15.flash_ctrl_wo.1275389435 |
|
|
Jul 07 06:17:08 PM PDT 24 |
Jul 07 06:20:51 PM PDT 24 |
3304456600 ps |
| T1105 |
/workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.2194261122 |
|
|
Jul 07 06:17:42 PM PDT 24 |
Jul 07 06:19:01 PM PDT 24 |
10019336900 ps |
| T1106 |
/workspace/coverage/default/29.flash_ctrl_connect.2004085994 |
|
|
Jul 07 06:18:41 PM PDT 24 |
Jul 07 06:18:57 PM PDT 24 |
42894200 ps |
| T1107 |
/workspace/coverage/default/18.flash_ctrl_prog_reset.3005085900 |
|
|
Jul 07 06:17:43 PM PDT 24 |
Jul 07 06:20:49 PM PDT 24 |
2250401000 ps |
| T1108 |
/workspace/coverage/default/9.flash_ctrl_intr_wr_slow_flash.820986599 |
|
|
Jul 07 06:15:57 PM PDT 24 |
Jul 07 06:18:52 PM PDT 24 |
20467861400 ps |
| T1109 |
/workspace/coverage/default/5.flash_ctrl_disable.401159358 |
|
|
Jul 07 06:15:07 PM PDT 24 |
Jul 07 06:15:29 PM PDT 24 |
11651200 ps |
| T1110 |
/workspace/coverage/default/0.flash_ctrl_integrity.4077730086 |
|
|
Jul 07 06:14:00 PM PDT 24 |
Jul 07 06:28:05 PM PDT 24 |
6611192600 ps |
| T1111 |
/workspace/coverage/default/10.flash_ctrl_smoke.3674155143 |
|
|
Jul 07 06:16:01 PM PDT 24 |
Jul 07 06:17:41 PM PDT 24 |
19385900 ps |
| T1112 |
/workspace/coverage/default/3.flash_ctrl_prog_reset.2688312090 |
|
|
Jul 07 06:14:27 PM PDT 24 |
Jul 07 06:14:41 PM PDT 24 |
19260700 ps |
| T1113 |
/workspace/coverage/default/7.flash_ctrl_otp_reset.610374048 |
|
|
Jul 07 06:15:19 PM PDT 24 |
Jul 07 06:17:33 PM PDT 24 |
37663300 ps |
| T1114 |
/workspace/coverage/default/29.flash_ctrl_prog_reset.4279926733 |
|
|
Jul 07 06:18:38 PM PDT 24 |
Jul 07 06:18:52 PM PDT 24 |
51290900 ps |
| T1115 |
/workspace/coverage/default/27.flash_ctrl_connect.3449438832 |
|
|
Jul 07 06:18:32 PM PDT 24 |
Jul 07 06:18:49 PM PDT 24 |
48508900 ps |
| T56 |
/workspace/coverage/default/3.flash_ctrl_fetch_code.114951836 |
|
|
Jul 07 06:14:23 PM PDT 24 |
Jul 07 06:14:51 PM PDT 24 |
1594080400 ps |
| T1116 |
/workspace/coverage/default/20.flash_ctrl_otp_reset.531430851 |
|
|
Jul 07 06:17:55 PM PDT 24 |
Jul 07 06:20:09 PM PDT 24 |
155215300 ps |
| T1117 |
/workspace/coverage/default/12.flash_ctrl_intr_rd.1413450573 |
|
|
Jul 07 06:16:29 PM PDT 24 |
Jul 07 06:19:04 PM PDT 24 |
1158352400 ps |
| T1118 |
/workspace/coverage/default/31.flash_ctrl_otp_reset.3128812930 |
|
|
Jul 07 06:18:51 PM PDT 24 |
Jul 07 06:21:05 PM PDT 24 |
145963100 ps |
| T1119 |
/workspace/coverage/default/16.flash_ctrl_invalid_op.1488784126 |
|
|
Jul 07 06:17:14 PM PDT 24 |
Jul 07 06:18:23 PM PDT 24 |
1696022000 ps |
| T1120 |
/workspace/coverage/default/12.flash_ctrl_alert_test.3534073684 |
|
|
Jul 07 06:16:41 PM PDT 24 |
Jul 07 06:16:55 PM PDT 24 |
46623200 ps |
| T1121 |
/workspace/coverage/default/49.flash_ctrl_otp_reset.4047979603 |
|
|
Jul 07 06:19:53 PM PDT 24 |
Jul 07 06:22:06 PM PDT 24 |
38641300 ps |
| T257 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.616418886 |
|
|
Jul 07 06:13:15 PM PDT 24 |
Jul 07 06:13:29 PM PDT 24 |
47656300 ps |
| T68 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.15978661 |
|
|
Jul 07 06:12:42 PM PDT 24 |
Jul 07 06:13:33 PM PDT 24 |
3185938300 ps |
| T258 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.3107463813 |
|
|
Jul 07 06:13:11 PM PDT 24 |
Jul 07 06:13:25 PM PDT 24 |
16462100 ps |
| T1122 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3613214630 |
|
|
Jul 07 06:12:46 PM PDT 24 |
Jul 07 06:13:02 PM PDT 24 |
21676700 ps |
| T69 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.21916343 |
|
|
Jul 07 06:13:04 PM PDT 24 |
Jul 07 06:13:23 PM PDT 24 |
181632500 ps |
| T70 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.3959340626 |
|
|
Jul 07 06:12:34 PM PDT 24 |
Jul 07 06:13:30 PM PDT 24 |
2402357700 ps |
| T199 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2478529687 |
|
|
Jul 07 06:12:33 PM PDT 24 |
Jul 07 06:13:13 PM PDT 24 |
114687800 ps |
| T99 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3802567296 |
|
|
Jul 07 06:12:48 PM PDT 24 |
Jul 07 06:19:12 PM PDT 24 |
308502800 ps |
| T100 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.675574666 |
|
|
Jul 07 06:12:45 PM PDT 24 |
Jul 07 06:13:03 PM PDT 24 |
88983900 ps |
| T326 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.888942927 |
|
|
Jul 07 06:13:16 PM PDT 24 |
Jul 07 06:13:30 PM PDT 24 |
65218000 ps |
| T198 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.3977093018 |
|
|
Jul 07 06:12:50 PM PDT 24 |
Jul 07 06:19:17 PM PDT 24 |
242158600 ps |
| T1123 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.204892564 |
|
|
Jul 07 06:13:04 PM PDT 24 |
Jul 07 06:13:21 PM PDT 24 |
62407200 ps |
| T197 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.3319935168 |
|
|
Jul 07 06:12:56 PM PDT 24 |
Jul 07 06:13:15 PM PDT 24 |
91956200 ps |
| T234 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.1281728297 |
|
|
Jul 07 06:12:44 PM PDT 24 |
Jul 07 06:27:45 PM PDT 24 |
1020502000 ps |
| T328 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.3942576399 |
|
|
Jul 07 06:12:31 PM PDT 24 |
Jul 07 06:12:45 PM PDT 24 |
39453200 ps |
| T327 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.935099249 |
|
|
Jul 07 06:13:14 PM PDT 24 |
Jul 07 06:13:28 PM PDT 24 |
51472900 ps |
| T302 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.1539767711 |
|
|
Jul 07 06:13:01 PM PDT 24 |
Jul 07 06:13:19 PM PDT 24 |
121861500 ps |
| T1124 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1899683187 |
|
|
Jul 07 06:13:03 PM PDT 24 |
Jul 07 06:13:17 PM PDT 24 |
15279300 ps |
| T1125 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.1577578306 |
|
|
Jul 07 06:13:15 PM PDT 24 |
Jul 07 06:13:29 PM PDT 24 |
70739600 ps |
| T329 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.2068494628 |
|
|
Jul 07 06:13:20 PM PDT 24 |
Jul 07 06:13:35 PM PDT 24 |
16684000 ps |
| T1126 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.1261850963 |
|
|
Jul 07 06:12:56 PM PDT 24 |
Jul 07 06:13:10 PM PDT 24 |
15820800 ps |
| T330 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.3284545997 |
|
|
Jul 07 06:13:12 PM PDT 24 |
Jul 07 06:13:26 PM PDT 24 |
54909600 ps |
| T331 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.2721852848 |
|
|
Jul 07 06:13:03 PM PDT 24 |
Jul 07 06:13:17 PM PDT 24 |
28304500 ps |
| T1127 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.536847176 |
|
|
Jul 07 06:13:00 PM PDT 24 |
Jul 07 06:13:16 PM PDT 24 |
12571400 ps |
| T306 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2976802477 |
|
|
Jul 07 06:13:06 PM PDT 24 |
Jul 07 06:13:23 PM PDT 24 |
86799800 ps |
| T241 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1495426361 |
|
|
Jul 07 06:12:38 PM PDT 24 |
Jul 07 06:20:15 PM PDT 24 |
2030966300 ps |
| T235 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.1050389145 |
|
|
Jul 07 06:12:59 PM PDT 24 |
Jul 07 06:13:18 PM PDT 24 |
80193400 ps |
| T236 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.1056852976 |
|
|
Jul 07 06:12:36 PM PDT 24 |
Jul 07 06:12:55 PM PDT 24 |
196991400 ps |
| T1128 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.359705234 |
|
|
Jul 07 06:12:55 PM PDT 24 |
Jul 07 06:13:12 PM PDT 24 |
93962300 ps |
| T307 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.3032104832 |
|
|
Jul 07 06:12:38 PM PDT 24 |
Jul 07 06:12:56 PM PDT 24 |
69329200 ps |
| T1129 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.377760846 |
|
|
Jul 07 06:12:59 PM PDT 24 |
Jul 07 06:13:15 PM PDT 24 |
161365300 ps |
| T1130 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.1746484289 |
|
|
Jul 07 06:13:07 PM PDT 24 |
Jul 07 06:13:27 PM PDT 24 |
627574300 ps |
| T1131 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.2878587354 |
|
|
Jul 07 06:12:38 PM PDT 24 |
Jul 07 06:12:52 PM PDT 24 |
86153700 ps |
| T237 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.2348370227 |
|
|
Jul 07 06:12:58 PM PDT 24 |
Jul 07 06:13:16 PM PDT 24 |
25799600 ps |
| T1132 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1856534369 |
|
|
Jul 07 06:12:36 PM PDT 24 |
Jul 07 06:12:49 PM PDT 24 |
22173500 ps |
| T238 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2601263797 |
|
|
Jul 07 06:12:49 PM PDT 24 |
Jul 07 06:13:07 PM PDT 24 |
54255600 ps |
| T1133 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.617424060 |
|
|
Jul 07 06:13:00 PM PDT 24 |
Jul 07 06:13:14 PM PDT 24 |
17316100 ps |
| T1134 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1809588206 |
|
|
Jul 07 06:12:46 PM PDT 24 |
Jul 07 06:13:03 PM PDT 24 |
221000400 ps |
| T1135 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.3526234525 |
|
|
Jul 07 06:12:44 PM PDT 24 |
Jul 07 06:13:15 PM PDT 24 |
92247900 ps |
| T1136 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.3361076013 |
|
|
Jul 07 06:13:12 PM PDT 24 |
Jul 07 06:13:25 PM PDT 24 |
17890300 ps |
| T1137 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3586644787 |
|
|
Jul 07 06:13:03 PM PDT 24 |
Jul 07 06:13:20 PM PDT 24 |
22920700 ps |
| T1138 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.2279238386 |
|
|
Jul 07 06:13:09 PM PDT 24 |
Jul 07 06:13:24 PM PDT 24 |
26180600 ps |
| T1139 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1300681310 |
|
|
Jul 07 06:12:59 PM PDT 24 |
Jul 07 06:13:17 PM PDT 24 |
31959900 ps |
| T1140 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.4271735057 |
|
|
Jul 07 06:12:40 PM PDT 24 |
Jul 07 06:12:57 PM PDT 24 |
15427600 ps |
| T1141 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.835187847 |
|
|
Jul 07 06:12:43 PM PDT 24 |
Jul 07 06:12:58 PM PDT 24 |
17456000 ps |
| T1142 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.761102760 |
|
|
Jul 07 06:12:43 PM PDT 24 |
Jul 07 06:12:57 PM PDT 24 |
14872400 ps |
| T362 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2565919652 |
|
|
Jul 07 06:12:45 PM PDT 24 |
Jul 07 06:14:05 PM PDT 24 |
3162808300 ps |
| T239 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3998802589 |
|
|
Jul 07 06:12:32 PM PDT 24 |
Jul 07 06:12:51 PM PDT 24 |
796488900 ps |
| T1143 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.3237914865 |
|
|
Jul 07 06:13:11 PM PDT 24 |
Jul 07 06:13:25 PM PDT 24 |
57795800 ps |
| T240 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.2826050008 |
|
|
Jul 07 06:12:41 PM PDT 24 |
Jul 07 06:27:45 PM PDT 24 |
2894617400 ps |
| T1144 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.4213641396 |
|
|
Jul 07 06:12:34 PM PDT 24 |
Jul 07 06:12:48 PM PDT 24 |
53338000 ps |
| T245 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.4061120285 |
|
|
Jul 07 06:12:34 PM PDT 24 |
Jul 07 06:12:48 PM PDT 24 |
44639300 ps |
| T1145 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.3205530877 |
|
|
Jul 07 06:13:01 PM PDT 24 |
Jul 07 06:13:17 PM PDT 24 |
37852500 ps |
| T271 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.2501210659 |
|
|
Jul 07 06:12:46 PM PDT 24 |
Jul 07 06:13:03 PM PDT 24 |
33785000 ps |
| T1146 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.2457685649 |
|
|
Jul 07 06:13:06 PM PDT 24 |
Jul 07 06:13:20 PM PDT 24 |
29261700 ps |
| T1147 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.89486684 |
|
|
Jul 07 06:12:37 PM PDT 24 |
Jul 07 06:12:51 PM PDT 24 |
43951500 ps |
| T1148 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3217681384 |
|
|
Jul 07 06:12:49 PM PDT 24 |
Jul 07 06:13:07 PM PDT 24 |
112705500 ps |
| T1149 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.301469024 |
|
|
Jul 07 06:12:45 PM PDT 24 |
Jul 07 06:13:04 PM PDT 24 |
1705864300 ps |
| T1150 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.500177103 |
|
|
Jul 07 06:13:12 PM PDT 24 |
Jul 07 06:13:26 PM PDT 24 |
16923700 ps |
| T352 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.285889210 |
|
|
Jul 07 06:13:03 PM PDT 24 |
Jul 07 06:28:17 PM PDT 24 |
3920004500 ps |
| T1151 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3957376949 |
|
|
Jul 07 06:12:40 PM PDT 24 |
Jul 07 06:13:13 PM PDT 24 |
1261355200 ps |
| T1152 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.1342330817 |
|
|
Jul 07 06:12:35 PM PDT 24 |
Jul 07 06:12:51 PM PDT 24 |
25248700 ps |
| T1153 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.3839333970 |
|
|
Jul 07 06:12:46 PM PDT 24 |
Jul 07 06:13:01 PM PDT 24 |
17513000 ps |
| T1154 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.3166183841 |
|
|
Jul 07 06:13:10 PM PDT 24 |
Jul 07 06:13:24 PM PDT 24 |
24226200 ps |
| T1155 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.1529609674 |
|
|
Jul 07 06:12:58 PM PDT 24 |
Jul 07 06:13:13 PM PDT 24 |
178862100 ps |
| T1156 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.566165825 |
|
|
Jul 07 06:12:49 PM PDT 24 |
Jul 07 06:13:02 PM PDT 24 |
29151100 ps |
| T1157 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.3176888959 |
|
|
Jul 07 06:13:00 PM PDT 24 |
Jul 07 06:13:35 PM PDT 24 |
166381100 ps |
| T1158 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.3145281546 |
|
|
Jul 07 06:12:29 PM PDT 24 |
Jul 07 06:12:44 PM PDT 24 |
11143200 ps |
| T272 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2289973300 |
|
|
Jul 07 06:13:01 PM PDT 24 |
Jul 07 06:28:03 PM PDT 24 |
821089000 ps |
| T1159 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.3983913809 |
|
|
Jul 07 06:12:52 PM PDT 24 |
Jul 07 06:13:06 PM PDT 24 |
15580700 ps |
| T1160 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.3395258684 |
|
|
Jul 07 06:12:29 PM PDT 24 |
Jul 07 06:12:45 PM PDT 24 |
20806000 ps |
| T1161 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.615472978 |
|
|
Jul 07 06:13:14 PM PDT 24 |
Jul 07 06:13:27 PM PDT 24 |
29105700 ps |
| T303 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2843734698 |
|
|
Jul 07 06:12:57 PM PDT 24 |
Jul 07 06:13:14 PM PDT 24 |
85328100 ps |
| T353 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.3251075577 |
|
|
Jul 07 06:12:56 PM PDT 24 |
Jul 07 06:20:37 PM PDT 24 |
1819390300 ps |
| T252 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.4237194174 |
|
|
Jul 07 06:12:42 PM PDT 24 |
Jul 07 06:12:59 PM PDT 24 |
744285700 ps |
| T1162 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.4211103575 |
|
|
Jul 07 06:12:44 PM PDT 24 |
Jul 07 06:13:00 PM PDT 24 |
14418100 ps |
| T1163 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.1506174870 |
|
|
Jul 07 06:12:42 PM PDT 24 |
Jul 07 06:12:56 PM PDT 24 |
15103200 ps |
| T1164 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.561209925 |
|
|
Jul 07 06:12:56 PM PDT 24 |
Jul 07 06:13:13 PM PDT 24 |
52376100 ps |
| T274 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.3283057529 |
|
|
Jul 07 06:12:37 PM PDT 24 |
Jul 07 06:27:45 PM PDT 24 |
1455895500 ps |
| T254 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1562963042 |
|
|
Jul 07 06:12:41 PM PDT 24 |
Jul 07 06:12:55 PM PDT 24 |
47461700 ps |
| T1165 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.202098671 |
|
|
Jul 07 06:12:39 PM PDT 24 |
Jul 07 06:12:56 PM PDT 24 |
110734900 ps |
| T255 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.1776406543 |
|
|
Jul 07 06:12:37 PM PDT 24 |
Jul 07 06:27:45 PM PDT 24 |
344818900 ps |
| T1166 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.828154822 |
|
|
Jul 07 06:12:37 PM PDT 24 |
Jul 07 06:13:23 PM PDT 24 |
25610500 ps |
| T1167 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.271588119 |
|
|
Jul 07 06:13:17 PM PDT 24 |
Jul 07 06:13:31 PM PDT 24 |
72527100 ps |
| T1168 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2715664133 |
|
|
Jul 07 06:12:59 PM PDT 24 |
Jul 07 06:13:17 PM PDT 24 |
181725500 ps |
| T1169 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.737304889 |
|
|
Jul 07 06:12:52 PM PDT 24 |
Jul 07 06:13:05 PM PDT 24 |
34268100 ps |
| T1170 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1755851101 |
|
|
Jul 07 06:12:35 PM PDT 24 |
Jul 07 06:13:38 PM PDT 24 |
5002520500 ps |
| T268 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.32868854 |
|
|
Jul 07 06:12:56 PM PDT 24 |
Jul 07 06:13:16 PM PDT 24 |
691184300 ps |
| T1171 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2499376108 |
|
|
Jul 07 06:12:35 PM PDT 24 |
Jul 07 06:12:51 PM PDT 24 |
19009300 ps |
| T1172 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1049354228 |
|
|
Jul 07 06:13:00 PM PDT 24 |
Jul 07 06:13:17 PM PDT 24 |
18256400 ps |
| T1173 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.2426966485 |
|
|
Jul 07 06:12:59 PM PDT 24 |
Jul 07 06:13:13 PM PDT 24 |
17267100 ps |
| T350 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.2049249520 |
|
|
Jul 07 06:13:03 PM PDT 24 |
Jul 07 06:13:23 PM PDT 24 |
171797000 ps |
| T1174 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.1721807268 |
|
|
Jul 07 06:12:46 PM PDT 24 |
Jul 07 06:13:02 PM PDT 24 |
37722000 ps |
| T1175 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3258473030 |
|
|
Jul 07 06:12:34 PM PDT 24 |
Jul 07 06:13:21 PM PDT 24 |
2476657700 ps |
| T1176 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.4170495447 |
|
|
Jul 07 06:12:56 PM PDT 24 |
Jul 07 06:13:14 PM PDT 24 |
69872800 ps |
| T1177 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.2726801712 |
|
|
Jul 07 06:12:42 PM PDT 24 |
Jul 07 06:13:24 PM PDT 24 |
642724600 ps |
| T1178 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.1038795695 |
|
|
Jul 07 06:12:51 PM PDT 24 |
Jul 07 06:13:07 PM PDT 24 |
23850500 ps |
| T1179 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.3852405407 |
|
|
Jul 07 06:13:04 PM PDT 24 |
Jul 07 06:13:19 PM PDT 24 |
29763500 ps |
| T1180 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.1211082961 |
|
|
Jul 07 06:12:52 PM PDT 24 |
Jul 07 06:13:05 PM PDT 24 |
16632900 ps |
| T359 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.3008873437 |
|
|
Jul 07 06:12:56 PM PDT 24 |
Jul 07 06:25:35 PM PDT 24 |
873337200 ps |
| T1181 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.4043601762 |
|
|
Jul 07 06:12:50 PM PDT 24 |
Jul 07 06:13:06 PM PDT 24 |
33311300 ps |
| T1182 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2144029485 |
|
|
Jul 07 06:12:40 PM PDT 24 |
Jul 07 06:12:58 PM PDT 24 |
90485700 ps |
| T1183 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.3542433019 |
|
|
Jul 07 06:13:13 PM PDT 24 |
Jul 07 06:13:26 PM PDT 24 |
17044500 ps |
| T1184 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.1497847721 |
|
|
Jul 07 06:13:12 PM PDT 24 |
Jul 07 06:13:26 PM PDT 24 |
29117500 ps |
| T270 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.793534521 |
|
|
Jul 07 06:12:49 PM PDT 24 |
Jul 07 06:13:05 PM PDT 24 |
37371900 ps |
| T1185 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.1945154868 |
|
|
Jul 07 06:13:19 PM PDT 24 |
Jul 07 06:13:33 PM PDT 24 |
53139200 ps |
| T1186 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.3075641339 |
|
|
Jul 07 06:13:00 PM PDT 24 |
Jul 07 06:13:17 PM PDT 24 |
23690800 ps |
| T275 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.4009681626 |
|
|
Jul 07 06:12:55 PM PDT 24 |
Jul 07 06:13:15 PM PDT 24 |
355813600 ps |
| T1187 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.2397645649 |
|
|
Jul 07 06:12:46 PM PDT 24 |
Jul 07 06:13:00 PM PDT 24 |
57222100 ps |
| T1188 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.415394631 |
|
|
Jul 07 06:12:35 PM PDT 24 |
Jul 07 06:12:51 PM PDT 24 |
38678200 ps |
| T1189 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3912388573 |
|
|
Jul 07 06:12:56 PM PDT 24 |
Jul 07 06:13:14 PM PDT 24 |
468875000 ps |
| T1190 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2958907447 |
|
|
Jul 07 06:13:07 PM PDT 24 |
Jul 07 06:13:21 PM PDT 24 |
51381500 ps |
| T246 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1787629406 |
|
|
Jul 07 06:12:41 PM PDT 24 |
Jul 07 06:12:55 PM PDT 24 |
194136100 ps |
| T1191 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.353854774 |
|
|
Jul 07 06:12:39 PM PDT 24 |
Jul 07 06:12:55 PM PDT 24 |
20035300 ps |
| T1192 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.4220627318 |
|
|
Jul 07 06:12:45 PM PDT 24 |
Jul 07 06:13:21 PM PDT 24 |
330172200 ps |
| T1193 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.4035374965 |
|
|
Jul 07 06:13:02 PM PDT 24 |
Jul 07 06:13:32 PM PDT 24 |
119091500 ps |
| T304 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2971749871 |
|
|
Jul 07 06:12:53 PM PDT 24 |
Jul 07 06:13:11 PM PDT 24 |
355351900 ps |
| T1194 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.1849748110 |
|
|
Jul 07 06:13:13 PM PDT 24 |
Jul 07 06:13:27 PM PDT 24 |
15298100 ps |
| T305 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1476022520 |
|
|
Jul 07 06:12:50 PM PDT 24 |
Jul 07 06:13:07 PM PDT 24 |
540510200 ps |
| T1195 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.2711903681 |
|
|
Jul 07 06:13:09 PM PDT 24 |
Jul 07 06:13:23 PM PDT 24 |
63763900 ps |
| T1196 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.3513343106 |
|
|
Jul 07 06:12:42 PM PDT 24 |
Jul 07 06:13:00 PM PDT 24 |
502402400 ps |
| T259 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.454231226 |
|
|
Jul 07 06:13:06 PM PDT 24 |
Jul 07 06:13:25 PM PDT 24 |
125607400 ps |
| T261 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.3209943066 |
|
|
Jul 07 06:12:51 PM PDT 24 |
Jul 07 06:13:09 PM PDT 24 |
184102100 ps |
| T355 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.59977448 |
|
|
Jul 07 06:12:50 PM PDT 24 |
Jul 07 06:27:53 PM PDT 24 |
1570112500 ps |
| T1197 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3001174245 |
|
|
Jul 07 06:12:57 PM PDT 24 |
Jul 07 06:13:14 PM PDT 24 |
35601500 ps |
| T1198 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.4223209792 |
|
|
Jul 07 06:13:00 PM PDT 24 |
Jul 07 06:19:28 PM PDT 24 |
395348900 ps |
| T247 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.3859336816 |
|
|
Jul 07 06:12:43 PM PDT 24 |
Jul 07 06:12:57 PM PDT 24 |
32097200 ps |
| T308 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.3652523828 |
|
|
Jul 07 06:12:45 PM PDT 24 |
Jul 07 06:13:00 PM PDT 24 |
65433600 ps |
| T1199 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2891328104 |
|
|
Jul 07 06:12:56 PM PDT 24 |
Jul 07 06:13:13 PM PDT 24 |
828813700 ps |
| T1200 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.3598525081 |
|
|
Jul 07 06:12:51 PM PDT 24 |
Jul 07 06:13:07 PM PDT 24 |
30647400 ps |
| T1201 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1916095715 |
|
|
Jul 07 06:12:54 PM PDT 24 |
Jul 07 06:13:31 PM PDT 24 |
1018407400 ps |
| T1202 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.2496243906 |
|
|
Jul 07 06:12:30 PM PDT 24 |
Jul 07 06:12:50 PM PDT 24 |
163901800 ps |
| T260 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.521725727 |
|
|
Jul 07 06:13:03 PM PDT 24 |
Jul 07 06:13:20 PM PDT 24 |
144098300 ps |
| T1203 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.3419620331 |
|
|
Jul 07 06:13:01 PM PDT 24 |
Jul 07 06:13:17 PM PDT 24 |
12488900 ps |
| T1204 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.3901723679 |
|
|
Jul 07 06:12:57 PM PDT 24 |
Jul 07 06:13:15 PM PDT 24 |
38730900 ps |
| T265 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.1304373793 |
|
|
Jul 07 06:12:54 PM PDT 24 |
Jul 07 06:13:11 PM PDT 24 |
124984400 ps |
| T309 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.91097516 |
|
|
Jul 07 06:13:04 PM PDT 24 |
Jul 07 06:13:23 PM PDT 24 |
99294100 ps |
| T262 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.4106965818 |
|
|
Jul 07 06:12:49 PM PDT 24 |
Jul 07 06:13:07 PM PDT 24 |
51492000 ps |
| T1205 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.2343747193 |
|
|
Jul 07 06:13:16 PM PDT 24 |
Jul 07 06:13:29 PM PDT 24 |
244207300 ps |
| T1206 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.653533323 |
|
|
Jul 07 06:13:10 PM PDT 24 |
Jul 07 06:13:24 PM PDT 24 |
54429100 ps |
| T1207 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.2741879037 |
|
|
Jul 07 06:12:42 PM PDT 24 |
Jul 07 06:13:00 PM PDT 24 |
168220600 ps |
| T1208 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2491555441 |
|
|
Jul 07 06:12:50 PM PDT 24 |
Jul 07 06:13:27 PM PDT 24 |
157206400 ps |
| T1209 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.2337716977 |
|
|
Jul 07 06:13:00 PM PDT 24 |
Jul 07 06:13:14 PM PDT 24 |
18215600 ps |
| T1210 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.3475319379 |
|
|
Jul 07 06:13:20 PM PDT 24 |
Jul 07 06:13:35 PM PDT 24 |
48079800 ps |
| T256 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.643750917 |
|
|
Jul 07 06:13:00 PM PDT 24 |
Jul 07 06:13:19 PM PDT 24 |
34469200 ps |
| T269 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.166676069 |
|
|
Jul 07 06:13:03 PM PDT 24 |
Jul 07 06:13:22 PM PDT 24 |
448505700 ps |
| T1211 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.905457477 |
|
|
Jul 07 06:12:34 PM PDT 24 |
Jul 07 06:13:20 PM PDT 24 |
2411693500 ps |
| T1212 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.3044401793 |
|
|
Jul 07 06:12:46 PM PDT 24 |
Jul 07 06:13:00 PM PDT 24 |
20013200 ps |
| T1213 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.2081151350 |
|
|
Jul 07 06:13:05 PM PDT 24 |
Jul 07 06:13:19 PM PDT 24 |
25356500 ps |
| T1214 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1464234500 |
|
|
Jul 07 06:13:02 PM PDT 24 |
Jul 07 06:13:19 PM PDT 24 |
59348600 ps |
| T1215 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.1464557214 |
|
|
Jul 07 06:12:42 PM PDT 24 |
Jul 07 06:12:56 PM PDT 24 |
23652500 ps |
| T1216 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.1111836397 |
|
|
Jul 07 06:13:06 PM PDT 24 |
Jul 07 06:13:21 PM PDT 24 |
14275600 ps |
| T1217 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.3769156652 |
|
|
Jul 07 06:12:47 PM PDT 24 |
Jul 07 06:13:03 PM PDT 24 |
33242600 ps |
| T1218 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2521953605 |
|
|
Jul 07 06:12:58 PM PDT 24 |
Jul 07 06:13:11 PM PDT 24 |
26613400 ps |
| T354 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2722256999 |
|
|
Jul 07 06:12:53 PM PDT 24 |
Jul 07 06:25:41 PM PDT 24 |
687143700 ps |
| T1219 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3502629639 |
|
|
Jul 07 06:12:48 PM PDT 24 |
Jul 07 06:13:06 PM PDT 24 |
69540400 ps |
| T1220 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.4155656678 |
|
|
Jul 07 06:13:13 PM PDT 24 |
Jul 07 06:13:27 PM PDT 24 |
21400400 ps |
| T1221 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2801613355 |
|
|
Jul 07 06:13:00 PM PDT 24 |
Jul 07 06:13:18 PM PDT 24 |
132689200 ps |
| T356 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.1235358423 |
|
|
Jul 07 06:13:03 PM PDT 24 |
Jul 07 06:19:33 PM PDT 24 |
1688786600 ps |
| T1222 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.695657668 |
|
|
Jul 07 06:13:09 PM PDT 24 |
Jul 07 06:20:47 PM PDT 24 |
364907900 ps |
| T1223 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.1291650012 |
|
|
Jul 07 06:13:11 PM PDT 24 |
Jul 07 06:13:25 PM PDT 24 |
47981300 ps |
| T1224 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.163128951 |
|
|
Jul 07 06:13:17 PM PDT 24 |
Jul 07 06:13:31 PM PDT 24 |
49796100 ps |
| T1225 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.1107099701 |
|
|
Jul 07 06:13:06 PM PDT 24 |
Jul 07 06:13:21 PM PDT 24 |
15255400 ps |
| T1226 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.190047157 |
|
|
Jul 07 06:13:17 PM PDT 24 |
Jul 07 06:13:31 PM PDT 24 |
186302500 ps |
| T1227 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.2979170555 |
|
|
Jul 07 06:12:43 PM PDT 24 |
Jul 07 06:13:15 PM PDT 24 |
109652300 ps |
| T248 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1396182771 |
|
|
Jul 07 06:12:37 PM PDT 24 |
Jul 07 06:12:51 PM PDT 24 |
31606400 ps |
| T1228 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1121929650 |
|
|
Jul 07 06:13:05 PM PDT 24 |
Jul 07 06:13:41 PM PDT 24 |
269081400 ps |
| T1229 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.922777179 |
|
|
Jul 07 06:12:38 PM PDT 24 |
Jul 07 06:13:18 PM PDT 24 |
1302837500 ps |
| T1230 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.1992051937 |
|
|
Jul 07 06:13:18 PM PDT 24 |
Jul 07 06:13:31 PM PDT 24 |
57703500 ps |
| T310 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.4088858909 |
|
|
Jul 07 06:13:05 PM PDT 24 |
Jul 07 06:13:41 PM PDT 24 |
199274600 ps |
| T1231 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.1915209262 |
|
|
Jul 07 06:12:56 PM PDT 24 |
Jul 07 06:13:13 PM PDT 24 |
22117300 ps |
| T273 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.1442834011 |
|
|
Jul 07 06:12:46 PM PDT 24 |
Jul 07 06:13:04 PM PDT 24 |
210648500 ps |
| T311 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.606045583 |
|
|
Jul 07 06:12:40 PM PDT 24 |
Jul 07 06:12:57 PM PDT 24 |
183737800 ps |
| T1232 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.1360567231 |
|
|
Jul 07 06:12:30 PM PDT 24 |
Jul 07 06:18:59 PM PDT 24 |
1320587300 ps |
| T1233 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2271168956 |
|
|
Jul 07 06:12:54 PM PDT 24 |
Jul 07 06:13:07 PM PDT 24 |
19593200 ps |
| T1234 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2128844239 |
|
|
Jul 07 06:12:55 PM PDT 24 |
Jul 07 06:13:08 PM PDT 24 |
13249300 ps |
| T1235 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2642562259 |
|
|
Jul 07 06:12:54 PM PDT 24 |
Jul 07 06:13:10 PM PDT 24 |
16339800 ps |
| T357 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.175573887 |
|
|
Jul 07 06:12:57 PM PDT 24 |
Jul 07 06:25:30 PM PDT 24 |
807614200 ps |
| T263 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.3214831608 |
|
|
Jul 07 06:12:42 PM PDT 24 |
Jul 07 06:13:00 PM PDT 24 |
36990300 ps |
| T1236 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.1771540989 |
|
|
Jul 07 06:12:41 PM PDT 24 |
Jul 07 06:12:57 PM PDT 24 |
149169700 ps |
| T351 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.3891924074 |
|
|
Jul 07 06:12:42 PM PDT 24 |
Jul 07 06:13:00 PM PDT 24 |
104302500 ps |
| T1237 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.3404031037 |
|
|
Jul 07 06:13:17 PM PDT 24 |
Jul 07 06:13:31 PM PDT 24 |
37154300 ps |
| T264 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.3585015011 |
|
|
Jul 07 06:12:56 PM PDT 24 |
Jul 07 06:13:15 PM PDT 24 |
251878300 ps |
| T1238 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.1627717791 |
|
|
Jul 07 06:12:45 PM PDT 24 |
Jul 07 06:12:59 PM PDT 24 |
17495300 ps |
| T1239 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.658765878 |
|
|
Jul 07 06:12:29 PM PDT 24 |
Jul 07 06:12:43 PM PDT 24 |
14798300 ps |
| T1240 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.2412075513 |
|
|
Jul 07 06:12:42 PM PDT 24 |
Jul 07 06:13:02 PM PDT 24 |
194104100 ps |
| T1241 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.3544622320 |
|
|
Jul 07 06:12:43 PM PDT 24 |
Jul 07 06:13:01 PM PDT 24 |
127447200 ps |
| T1242 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.1502255220 |
|
|
Jul 07 06:12:44 PM PDT 24 |
Jul 07 06:12:57 PM PDT 24 |
17825200 ps |
| T1243 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1612123700 |
|
|
Jul 07 06:13:13 PM PDT 24 |
Jul 07 06:13:27 PM PDT 24 |
31192400 ps |
| T1244 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3554095308 |
|
|
Jul 07 06:13:06 PM PDT 24 |
Jul 07 06:13:20 PM PDT 24 |
19716700 ps |
| T266 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1394801373 |
|
|
Jul 07 06:12:34 PM PDT 24 |
Jul 07 06:12:50 PM PDT 24 |
75580900 ps |
| T1245 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.3882000680 |
|
|
Jul 07 06:12:51 PM PDT 24 |
Jul 07 06:13:06 PM PDT 24 |
26964500 ps |
| T1246 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3480626391 |
|
|
Jul 07 06:12:30 PM PDT 24 |
Jul 07 06:12:50 PM PDT 24 |
76830300 ps |
| T1247 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3662289000 |
|
|
Jul 07 06:12:35 PM PDT 24 |
Jul 07 06:13:05 PM PDT 24 |
19874200 ps |
| T1248 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.4011277097 |
|
|
Jul 07 06:12:48 PM PDT 24 |
Jul 07 06:13:05 PM PDT 24 |
206527400 ps |
| T1249 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.3732783655 |
|
|
Jul 07 06:12:54 PM PDT 24 |
Jul 07 06:13:11 PM PDT 24 |
33005100 ps |
| T1250 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1592783272 |
|
|
Jul 07 06:12:56 PM PDT 24 |
Jul 07 06:13:11 PM PDT 24 |
13214300 ps |
| T1251 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2907602688 |
|
|
Jul 07 06:12:55 PM PDT 24 |
Jul 07 06:13:12 PM PDT 24 |
37611300 ps |
| T1252 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.3674261442 |
|
|
Jul 07 06:13:12 PM PDT 24 |
Jul 07 06:13:27 PM PDT 24 |
53479700 ps |
| T1253 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.4203087164 |
|
|
Jul 07 06:12:45 PM PDT 24 |
Jul 07 06:13:02 PM PDT 24 |
569542100 ps |