Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	322958	1		T1	2		T2	2		T3	1
all_values[1]	322958	1		T1	2		T2	2		T3	1
all_values[2]	322958	1		T1	2		T2	2		T3	1
all_values[3]	322958	1		T1	2		T2	2		T3	1
all_values[4]	322958	1		T1	2		T2	2		T3	1
all_values[5]	322958	1		T1	2		T2	2		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	652103	1		T1	12		T2	12		T3	6
auto[1]	1285645	1		T5	12632		T6	13136		T21	25296

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	946197	1		T1	7		T2	7		T3	4
auto[1]	991551	1		T1	5		T2	5		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	322821	1		T1	2		T2	2		T3	1
all_values[0]	auto[1]	auto[1]	137	1		T244	5		T245	1		T246	2
all_values[1]	auto[0]	auto[1]	322779	1		T1	2		T2	2		T3	1
all_values[1]	auto[1]	auto[1]	179	1		T244	7		T245	4		T246	1
all_values[2]	auto[0]	auto[0]	1583	1		T1	2		T2	2		T3	1
all_values[2]	auto[0]	auto[1]	48	1		T244	1		T246	1		T317	1
all_values[2]	auto[1]	auto[0]	321277	1		T5	3158		T6	3284		T21	6324
all_values[2]	auto[1]	auto[1]	50	1		T244	1		T245	2		T246	1
all_values[3]	auto[0]	auto[0]	1561	1		T1	2		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	49	1		T244	2		T246	1		T316	1
all_values[3]	auto[1]	auto[0]	88983	1		T5	1579		T6	1642		T21	1581
all_values[3]	auto[1]	auto[1]	232365	1		T5	1579		T6	1642		T21	4743
all_values[4]	auto[0]	auto[0]	1105	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	515	1		T1	1		T2	1		T4	1
all_values[4]	auto[1]	auto[0]	208915	1		T5	1579		T6	1642		T21	4743
all_values[4]	auto[1]	auto[1]	112423	1		T5	1579		T6	1642		T21	1581
all_values[5]	auto[0]	auto[0]	1520	1		T1	2		T2	2		T3	1
all_values[5]	auto[0]	auto[1]	122	1		T22	1		T37	1		T38	1
all_values[5]	auto[1]	auto[0]	321253	1		T5	3158		T6	3284		T21	6324
all_values[5]	auto[1]	auto[1]	63	1		T244	4		T246	1		T316	1