Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	243369	1		T1	17		T2	553		T3	373
auto[FlashEraseBank]	274235	1		T1	4		T2	717		T4	3

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	263846	1		T1	8		T3	181		T4	2
auto[FlashOpProgram]	234687	1		T1	4		T2	1270		T3	96
auto[FlashOpErase]	15071	1		T1	9		T3	96		T20	19
auto[FlashOpInvalid]	4000	1		T62	200		T145	200		T256	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	263846	1		T1	8		T3	181		T4	2
op[FlashOpProgram]	234687	1		T1	4		T2	1270		T3	96
op[FlashOpErase]	15071	1		T1	9		T3	96		T20	19
read_erase_read	546	1		T1	2		T20	11		T32	3
read_prog_read	926	1		T22	1		T26	7		T55	8

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	382029	1		T1	20		T2	1050		T4	4
auto[FlashPartInfo]	132266	1		T1	1		T2	209		T3	373
auto[FlashPartInfo1]	805	1		T42	4		T62	6		T23	3
auto[FlashPartInfo2]	2504	1		T2	11		T20	8		T26	4

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	196527	1		T1	7		T4	2		T5	1579
auto[FlashPartData]	auto[FlashOpProgram]	177976	1		T1	4		T2	1050		T4	2
auto[FlashPartData]	auto[FlashOpErase]	3582	1		T1	9		T20	10		T62	98
auto[FlashPartData]	auto[FlashOpInvalid]	3944	1		T62	196		T145	196		T256	198
auto[FlashPartInfo]	auto[FlashOpRead]	65120	1		T1	1		T3	181		T20	16
auto[FlashPartInfo]	auto[FlashOpProgram]	55645	1		T2	209		T3	96		T22	62
auto[FlashPartInfo]	auto[FlashOpErase]	11455	1		T3	96		T20	6		T62	1
auto[FlashPartInfo]	auto[FlashOpInvalid]	46	1		T62	2		T145	2		T256	2
auto[FlashPartInfo1]	auto[FlashOpRead]	629	1		T42	4		T62	2		T23	3
auto[FlashPartInfo1]	auto[FlashOpProgram]	166	1		T62	1		T32	1		T65	32
auto[FlashPartInfo1]	auto[FlashOpErase]	6	1		T62	1		T32	1		T130	2
auto[FlashPartInfo1]	auto[FlashOpInvalid]	4	1		T62	2		T399	2		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1570	1		T20	5		T26	3		T42	4
auto[FlashPartInfo2]	auto[FlashOpProgram]	900	1		T2	11		T26	1		T55	6
auto[FlashPartInfo2]	auto[FlashOpErase]	28	1		T20	3		T145	1		T220	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	6	1		T145	2		T152	2		T400	2