Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29676	1		T1	5		T3	204		T62	400
auto[1]	54	1		T87	1		T401	1		T402	3
auto[2]	71	1		T26	2		T60	8		T28	2
auto[3]	219	1		T20	11		T26	1		T29	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7518	1		T1	1		T3	51		T20	4
evic_idx[1]	7509	1		T1	1		T3	51		T20	2
evic_idx[2]	7494	1		T1	1		T3	51		T20	3
evic_idx[3]	7499	1		T1	2		T3	51		T20	2

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	29120	1		T3	204		T20	11		T62	400
evic_op[2]	344	1		T1	1		T26	3		T32	4

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7217	1		T3	51		T62	100		T102	60
evic_idx[0]	evic_op[1]	auto[1]	13	1		T402	1		T403	3		T404	1
evic_idx[0]	evic_op[1]	auto[2]	10	1		T405	2		T403	2		T404	4
evic_idx[0]	evic_op[1]	auto[3]	52	1		T20	4		T406	4		T402	2
evic_idx[0]	evic_op[2]	auto[0]	70	1		T32	1		T354	1		T407	10
evic_idx[0]	evic_op[2]	auto[1]	2	1		T401	1		T408	1		-	-
evic_idx[0]	evic_op[2]	auto[2]	1	1		T409	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[3]	14	1		T26	1		T29	1		T410	1
evic_idx[1]	evic_op[1]	auto[0]	7217	1		T3	51		T62	100		T102	60
evic_idx[1]	evic_op[1]	auto[1]	11	1		T402	1		T403	3		T404	1
evic_idx[1]	evic_op[1]	auto[2]	9	1		T405	2		T403	2		T404	2
evic_idx[1]	evic_op[1]	auto[3]	44	1		T20	2		T406	3		T402	1
evic_idx[1]	evic_op[2]	auto[0]	69	1		T32	1		T354	1		T407	10
evic_idx[1]	evic_op[2]	auto[1]	2	1		T87	1		T408	1		-	-
evic_idx[1]	evic_op[2]	auto[2]	7	1		T26	2		T411	1		T412	1
evic_idx[1]	evic_op[2]	auto[3]	11	1		T266	1		T413	1		T267	1
evic_idx[2]	evic_op[1]	auto[0]	7214	1		T3	51		T62	100		T102	60
evic_idx[2]	evic_op[1]	auto[1]	11	1		T405	1		T403	4		T404	1
evic_idx[2]	evic_op[1]	auto[2]	10	1		T405	2		T403	1		T404	2
evic_idx[2]	evic_op[1]	auto[3]	40	1		T20	3		T406	3		T402	1
evic_idx[2]	evic_op[2]	auto[0]	69	1		T32	1		T147	1		T354	1
evic_idx[2]	evic_op[2]	auto[1]	1	1		T414	1		-	-		-	-
evic_idx[2]	evic_op[2]	auto[2]	4	1		T28	1		T412	1		T415	1
evic_idx[2]	evic_op[2]	auto[3]	6	1		T416	1		T417	1		T263	1
evic_idx[3]	evic_op[1]	auto[0]	7213	1		T3	51		T62	100		T102	60
evic_idx[3]	evic_op[1]	auto[1]	11	1		T402	1		T403	3		T418	4
evic_idx[3]	evic_op[1]	auto[2]	7	1		T405	2		T403	1		T404	2
evic_idx[3]	evic_op[1]	auto[3]	41	1		T20	2		T406	3		T402	2
evic_idx[3]	evic_op[2]	auto[0]	71	1		T1	1		T32	1		T354	1
evic_idx[3]	evic_op[2]	auto[1]	3	1		T419	1		T420	1		T421	1
evic_idx[3]	evic_op[2]	auto[2]	3	1		T28	1		T411	1		T422	1
evic_idx[3]	evic_op[2]	auto[3]	11	1		T209	1		T40	1		T366	1