Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	6440	1		T56	1916		T322	2918		T323	1606
rd_lvl[2]	54580	1		T56	685		T59	2525		T92	12082
rd_lvl[3]	17334	1		T56	203		T59	1950		T92	383
rd_lvl[4]	22351	1		T56	345		T59	1118		T92	1
rd_lvl[5]	21979	1		T21	2315		T56	197		T59	1650
rd_lvl[6]	27402	1		T21	2428		T56	1		T59	2652
rd_lvl[7]	7087	1		T56	188		T59	93		T324	621
rd_lvl[8]	14441	1		T56	187		T59	93		T325	1173
rd_lvl[9]	6549	1		T56	291		T59	93		T324	1
rd_lvl[10]	7079	1		T5	1149		T56	85		T326	1
rd_lvl[11]	5921	1		T5	429		T6	775		T56	129
rd_lvl[12]	4151	1		T6	867		T56	2		T327	1041
rd_lvl[13]	2196	1		T5	1		T328	21		T329	214
rd_lvl[14]	14132	1		T56	126		T35	1281		T36	211
rd_lvl[15]	6576	1		T35	249		T36	167		T296	370