Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	322958	1		T1	2		T2	2		T3	1
all_pins[1]	322958	1		T1	2		T2	2		T3	1
all_pins[2]	322958	1		T1	2		T2	2		T3	1
all_pins[3]	322958	1		T1	2		T2	2		T3	1
all_pins[4]	322958	1		T1	2		T2	2		T3	1
all_pins[5]	322958	1		T1	2		T2	2		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1585840	1		T1	12		T2	12		T3	6
values[0x1]	351908	1		T5	3158		T6	3284		T21	7377
transitions[0x0=>0x1]	312853	1		T5	3158		T6	3284		T21	6324
transitions[0x1=>0x0]	312844	1		T5	3158		T6	3284		T21	6324

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	322821	1		T1	2		T2	2		T3	1
all_pins[0]	values[0x1]	137	1		T244	5		T245	1		T246	2
all_pins[0]	transitions[0x0=>0x1]	57	1		T244	1		T246	2		T315	2
all_pins[0]	transitions[0x1=>0x0]	99	1		T244	3		T245	3		T246	1
all_pins[1]	values[0x0]	322779	1		T1	2		T2	2		T3	1
all_pins[1]	values[0x1]	179	1		T244	7		T245	4		T246	1
all_pins[1]	transitions[0x0=>0x1]	152	1		T244	6		T245	2		T316	1
all_pins[1]	transitions[0x1=>0x0]	5069	1		T36	149		T332	1116		T333	88
all_pins[2]	values[0x0]	317862	1		T1	2		T2	2		T3	1
all_pins[2]	values[0x1]	5096	1		T36	149		T332	1116		T333	88
all_pins[2]	transitions[0x0=>0x1]	33	1		T245	2		T246	1		T316	1
all_pins[2]	transitions[0x1=>0x0]	218315	1		T5	1579		T6	1642		T21	4743
all_pins[3]	values[0x0]	99580	1		T1	2		T2	2		T3	1
all_pins[3]	values[0x1]	223378	1		T5	1579		T6	1642		T21	4743
all_pins[3]	transitions[0x0=>0x1]	189543	1		T5	1579		T6	1642		T21	3690
all_pins[3]	transitions[0x1=>0x0]	89220	1		T5	1579		T6	1642		T21	1581
all_pins[4]	values[0x0]	199903	1		T1	2		T2	2		T3	1
all_pins[4]	values[0x1]	123055	1		T5	1579		T6	1642		T21	2634
all_pins[4]	transitions[0x0=>0x1]	123037	1		T5	1579		T6	1642		T21	2634
all_pins[4]	transitions[0x1=>0x0]	45	1		T244	4		T315	1		T318	1
all_pins[5]	values[0x0]	322895	1		T1	2		T2	2		T3	1
all_pins[5]	values[0x1]	63	1		T244	4		T246	1		T316	1
all_pins[5]	transitions[0x0=>0x1]	31	1		T244	3		T246	1		T319	1
all_pins[5]	transitions[0x1=>0x0]	96	1		T244	4		T245	1		T246	2