| T1070 |
/workspace/coverage/default/28.flash_ctrl_rw_evict.2018675600 |
|
|
Jul 09 05:34:25 PM PDT 24 |
Jul 09 05:34:56 PM PDT 24 |
116125000 ps |
| T1071 |
/workspace/coverage/default/1.flash_ctrl_re_evict.914596794 |
|
|
Jul 09 05:31:14 PM PDT 24 |
Jul 09 05:31:46 PM PDT 24 |
124991300 ps |
| T1072 |
/workspace/coverage/default/18.flash_ctrl_prog_reset.1103187118 |
|
|
Jul 09 05:33:34 PM PDT 24 |
Jul 09 05:33:48 PM PDT 24 |
31623600 ps |
| T1073 |
/workspace/coverage/default/9.flash_ctrl_alert_test.3028852814 |
|
|
Jul 09 05:32:25 PM PDT 24 |
Jul 09 05:32:40 PM PDT 24 |
22485200 ps |
| T1074 |
/workspace/coverage/default/36.flash_ctrl_disable.1514109143 |
|
|
Jul 09 05:34:51 PM PDT 24 |
Jul 09 05:35:14 PM PDT 24 |
14131300 ps |
| T1075 |
/workspace/coverage/default/2.flash_ctrl_stress_all.2098638308 |
|
|
Jul 09 05:31:17 PM PDT 24 |
Jul 09 05:31:58 PM PDT 24 |
66839400 ps |
| T1076 |
/workspace/coverage/default/7.flash_ctrl_disable.1582389831 |
|
|
Jul 09 05:32:07 PM PDT 24 |
Jul 09 05:32:29 PM PDT 24 |
16332600 ps |
| T1077 |
/workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.2683887101 |
|
|
Jul 09 05:31:31 PM PDT 24 |
Jul 09 05:31:53 PM PDT 24 |
23885700 ps |
| T1078 |
/workspace/coverage/default/10.flash_ctrl_otp_reset.3683038205 |
|
|
Jul 09 05:32:25 PM PDT 24 |
Jul 09 05:34:42 PM PDT 24 |
40330100 ps |
| T1079 |
/workspace/coverage/default/9.flash_ctrl_rw_serr.3623151249 |
|
|
Jul 09 05:32:18 PM PDT 24 |
Jul 09 05:40:49 PM PDT 24 |
3602289700 ps |
| T183 |
/workspace/coverage/default/2.flash_ctrl_rma_err.3015276804 |
|
|
Jul 09 05:31:20 PM PDT 24 |
Jul 09 05:48:34 PM PDT 24 |
142945285200 ps |
| T1080 |
/workspace/coverage/default/0.flash_ctrl_ro_derr.2777582068 |
|
|
Jul 09 05:31:01 PM PDT 24 |
Jul 09 05:33:17 PM PDT 24 |
1198823700 ps |
| T1081 |
/workspace/coverage/default/33.flash_ctrl_otp_reset.1312488361 |
|
|
Jul 09 05:34:40 PM PDT 24 |
Jul 09 05:36:54 PM PDT 24 |
38546900 ps |
| T1082 |
/workspace/coverage/default/29.flash_ctrl_disable.2317666520 |
|
|
Jul 09 05:34:29 PM PDT 24 |
Jul 09 05:34:52 PM PDT 24 |
15281600 ps |
| T1083 |
/workspace/coverage/default/3.flash_ctrl_invalid_op.1349900627 |
|
|
Jul 09 05:31:39 PM PDT 24 |
Jul 09 05:32:41 PM PDT 24 |
7618045900 ps |
| T1084 |
/workspace/coverage/default/21.flash_ctrl_rw_evict_all_en.3232579012 |
|
|
Jul 09 05:33:53 PM PDT 24 |
Jul 09 05:34:25 PM PDT 24 |
27588600 ps |
| T1085 |
/workspace/coverage/default/4.flash_ctrl_serr_counter.3200350181 |
|
|
Jul 09 05:31:39 PM PDT 24 |
Jul 09 05:33:07 PM PDT 24 |
9108904000 ps |
| T1086 |
/workspace/coverage/default/64.flash_ctrl_connect.3424751408 |
|
|
Jul 09 05:35:32 PM PDT 24 |
Jul 09 05:35:46 PM PDT 24 |
21077400 ps |
| T1087 |
/workspace/coverage/default/6.flash_ctrl_rw_evict.3150252729 |
|
|
Jul 09 05:31:56 PM PDT 24 |
Jul 09 05:32:28 PM PDT 24 |
73083600 ps |
| T1088 |
/workspace/coverage/default/32.flash_ctrl_alert_test.3999790186 |
|
|
Jul 09 05:34:41 PM PDT 24 |
Jul 09 05:34:55 PM PDT 24 |
314702700 ps |
| T1089 |
/workspace/coverage/default/32.flash_ctrl_disable.3432625763 |
|
|
Jul 09 05:34:41 PM PDT 24 |
Jul 09 05:35:03 PM PDT 24 |
11158200 ps |
| T163 |
/workspace/coverage/default/0.flash_ctrl_mid_op_rst.1350307001 |
|
|
Jul 09 05:30:56 PM PDT 24 |
Jul 09 05:32:07 PM PDT 24 |
1813155000 ps |
| T1090 |
/workspace/coverage/default/18.flash_ctrl_rand_ops.990478251 |
|
|
Jul 09 05:33:31 PM PDT 24 |
Jul 09 05:45:20 PM PDT 24 |
1600857700 ps |
| T1091 |
/workspace/coverage/default/26.flash_ctrl_smoke.471543300 |
|
|
Jul 09 05:34:09 PM PDT 24 |
Jul 09 05:35:48 PM PDT 24 |
45293900 ps |
| T1092 |
/workspace/coverage/default/1.flash_ctrl_wo.3479734984 |
|
|
Jul 09 05:31:04 PM PDT 24 |
Jul 09 05:33:46 PM PDT 24 |
6737706400 ps |
| T1093 |
/workspace/coverage/default/46.flash_ctrl_smoke.2518731368 |
|
|
Jul 09 05:35:18 PM PDT 24 |
Jul 09 05:37:19 PM PDT 24 |
87385200 ps |
| T1094 |
/workspace/coverage/default/0.flash_ctrl_write_word_sweep.1717605416 |
|
|
Jul 09 05:30:56 PM PDT 24 |
Jul 09 05:31:13 PM PDT 24 |
41890600 ps |
| T1095 |
/workspace/coverage/default/10.flash_ctrl_rw.2840610891 |
|
|
Jul 09 05:32:25 PM PDT 24 |
Jul 09 05:40:50 PM PDT 24 |
3745098200 ps |
| T1096 |
/workspace/coverage/default/26.flash_ctrl_otp_reset.626036449 |
|
|
Jul 09 05:34:16 PM PDT 24 |
Jul 09 05:36:27 PM PDT 24 |
143208300 ps |
| T1097 |
/workspace/coverage/default/28.flash_ctrl_prog_reset.2544002889 |
|
|
Jul 09 05:34:28 PM PDT 24 |
Jul 09 05:34:43 PM PDT 24 |
19395100 ps |
| T1098 |
/workspace/coverage/default/44.flash_ctrl_otp_reset.2169335836 |
|
|
Jul 09 05:35:13 PM PDT 24 |
Jul 09 05:37:26 PM PDT 24 |
70610500 ps |
| T391 |
/workspace/coverage/default/36.flash_ctrl_sec_info_access.4081944326 |
|
|
Jul 09 05:34:50 PM PDT 24 |
Jul 09 05:35:52 PM PDT 24 |
1127130000 ps |
| T54 |
/workspace/coverage/default/7.flash_ctrl_fetch_code.467647782 |
|
|
Jul 09 05:31:56 PM PDT 24 |
Jul 09 05:32:24 PM PDT 24 |
761957900 ps |
| T1099 |
/workspace/coverage/default/2.flash_ctrl_disable.1963596623 |
|
|
Jul 09 05:31:23 PM PDT 24 |
Jul 09 05:31:44 PM PDT 24 |
26224600 ps |
| T1100 |
/workspace/coverage/default/5.flash_ctrl_ro_derr.804270101 |
|
|
Jul 09 05:31:39 PM PDT 24 |
Jul 09 05:34:00 PM PDT 24 |
562507800 ps |
| T1101 |
/workspace/coverage/default/5.flash_ctrl_rw_evict.273457483 |
|
|
Jul 09 05:31:39 PM PDT 24 |
Jul 09 05:32:09 PM PDT 24 |
31449300 ps |
| T1102 |
/workspace/coverage/default/4.flash_ctrl_invalid_op.87569005 |
|
|
Jul 09 05:31:29 PM PDT 24 |
Jul 09 05:32:42 PM PDT 24 |
8332761200 ps |
| T1103 |
/workspace/coverage/default/22.flash_ctrl_smoke.3480304455 |
|
|
Jul 09 05:33:56 PM PDT 24 |
Jul 09 05:34:49 PM PDT 24 |
70147700 ps |
| T1104 |
/workspace/coverage/default/29.flash_ctrl_intr_rd.2540028592 |
|
|
Jul 09 05:34:29 PM PDT 24 |
Jul 09 05:36:37 PM PDT 24 |
751468200 ps |
| T1105 |
/workspace/coverage/default/7.flash_ctrl_rw_serr.1289630158 |
|
|
Jul 09 05:32:02 PM PDT 24 |
Jul 09 05:40:45 PM PDT 24 |
5364397600 ps |
| T1106 |
/workspace/coverage/default/1.flash_ctrl_ro_serr.2967764085 |
|
|
Jul 09 05:31:02 PM PDT 24 |
Jul 09 05:33:25 PM PDT 24 |
1485052300 ps |
| T1107 |
/workspace/coverage/default/0.flash_ctrl_sec_info_access.539746957 |
|
|
Jul 09 05:30:59 PM PDT 24 |
Jul 09 05:32:13 PM PDT 24 |
1968316500 ps |
| T1108 |
/workspace/coverage/default/18.flash_ctrl_connect.2869905753 |
|
|
Jul 09 05:33:36 PM PDT 24 |
Jul 09 05:33:49 PM PDT 24 |
22987300 ps |
| T1109 |
/workspace/coverage/default/6.flash_ctrl_rw_derr.776131192 |
|
|
Jul 09 05:31:50 PM PDT 24 |
Jul 09 05:44:17 PM PDT 24 |
5239455900 ps |
| T1110 |
/workspace/coverage/default/13.flash_ctrl_otp_reset.668498880 |
|
|
Jul 09 05:32:47 PM PDT 24 |
Jul 09 05:34:58 PM PDT 24 |
67584000 ps |
| T1111 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1461258766 |
|
|
Jul 09 05:27:48 PM PDT 24 |
Jul 09 05:28:05 PM PDT 24 |
13317800 ps |
| T110 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.1783150870 |
|
|
Jul 09 05:27:42 PM PDT 24 |
Jul 09 05:28:00 PM PDT 24 |
39220100 ps |
| T67 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1123943242 |
|
|
Jul 09 05:27:53 PM PDT 24 |
Jul 09 05:34:21 PM PDT 24 |
1462719700 ps |
| T1112 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.757759609 |
|
|
Jul 09 05:27:52 PM PDT 24 |
Jul 09 05:28:09 PM PDT 24 |
38874500 ps |
| T68 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2308162077 |
|
|
Jul 09 05:27:50 PM PDT 24 |
Jul 09 05:28:09 PM PDT 24 |
108107700 ps |
| T1113 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.212732778 |
|
|
Jul 09 05:27:31 PM PDT 24 |
Jul 09 05:27:45 PM PDT 24 |
173377300 ps |
| T244 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.2615875937 |
|
|
Jul 09 05:28:10 PM PDT 24 |
Jul 09 05:28:25 PM PDT 24 |
102122200 ps |
| T69 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2599253677 |
|
|
Jul 09 05:27:41 PM PDT 24 |
Jul 09 05:35:20 PM PDT 24 |
342350100 ps |
| T1114 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2091782206 |
|
|
Jul 09 05:27:43 PM PDT 24 |
Jul 09 05:27:59 PM PDT 24 |
28283000 ps |
| T1115 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.824305 |
|
|
Jul 09 05:27:47 PM PDT 24 |
Jul 09 05:28:01 PM PDT 24 |
76400700 ps |
| T212 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3518021030 |
|
|
Jul 09 05:27:39 PM PDT 24 |
Jul 09 05:42:48 PM PDT 24 |
478859300 ps |
| T213 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2131142355 |
|
|
Jul 09 05:27:44 PM PDT 24 |
Jul 09 05:35:32 PM PDT 24 |
189711200 ps |
| T245 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.333093277 |
|
|
Jul 09 05:27:56 PM PDT 24 |
Jul 09 05:28:12 PM PDT 24 |
166566500 ps |
| T1116 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.2012568349 |
|
|
Jul 09 05:27:52 PM PDT 24 |
Jul 09 05:28:09 PM PDT 24 |
123923200 ps |
| T276 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.3452338248 |
|
|
Jul 09 05:27:44 PM PDT 24 |
Jul 09 05:28:01 PM PDT 24 |
110558300 ps |
| T1117 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.3882009180 |
|
|
Jul 09 05:27:33 PM PDT 24 |
Jul 09 05:27:47 PM PDT 24 |
16987700 ps |
| T277 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1469301266 |
|
|
Jul 09 05:27:30 PM PDT 24 |
Jul 09 05:28:18 PM PDT 24 |
1757765700 ps |
| T1118 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.1333156482 |
|
|
Jul 09 05:27:50 PM PDT 24 |
Jul 09 05:28:27 PM PDT 24 |
58742200 ps |
| T211 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.1802144787 |
|
|
Jul 09 05:27:50 PM PDT 24 |
Jul 09 05:28:10 PM PDT 24 |
254411900 ps |
| T278 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1237620479 |
|
|
Jul 09 05:27:56 PM PDT 24 |
Jul 09 05:28:16 PM PDT 24 |
305568300 ps |
| T246 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.2052565399 |
|
|
Jul 09 05:27:55 PM PDT 24 |
Jul 09 05:28:10 PM PDT 24 |
47095600 ps |
| T225 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.2666613420 |
|
|
Jul 09 05:27:33 PM PDT 24 |
Jul 09 05:27:52 PM PDT 24 |
41152700 ps |
| T279 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.775568806 |
|
|
Jul 09 05:27:40 PM PDT 24 |
Jul 09 05:28:13 PM PDT 24 |
450431300 ps |
| T316 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.2289925574 |
|
|
Jul 09 05:27:55 PM PDT 24 |
Jul 09 05:28:09 PM PDT 24 |
57913100 ps |
| T233 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1101837231 |
|
|
Jul 09 05:27:31 PM PDT 24 |
Jul 09 05:27:45 PM PDT 24 |
32266600 ps |
| T1119 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3806191494 |
|
|
Jul 09 05:27:55 PM PDT 24 |
Jul 09 05:28:10 PM PDT 24 |
13656300 ps |
| T1120 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2922887416 |
|
|
Jul 09 05:27:35 PM PDT 24 |
Jul 09 05:27:52 PM PDT 24 |
69170700 ps |
| T317 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3263227797 |
|
|
Jul 09 05:27:56 PM PDT 24 |
Jul 09 05:28:11 PM PDT 24 |
55526200 ps |
| T315 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2828893173 |
|
|
Jul 09 05:28:07 PM PDT 24 |
Jul 09 05:28:23 PM PDT 24 |
105850900 ps |
| T226 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.2430191495 |
|
|
Jul 09 05:27:54 PM PDT 24 |
Jul 09 05:28:15 PM PDT 24 |
86208800 ps |
| T234 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.1417069871 |
|
|
Jul 09 05:27:32 PM PDT 24 |
Jul 09 05:27:47 PM PDT 24 |
28525400 ps |
| T318 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.316049592 |
|
|
Jul 09 05:28:04 PM PDT 24 |
Jul 09 05:28:19 PM PDT 24 |
29833700 ps |
| T319 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.3697293826 |
|
|
Jul 09 05:27:54 PM PDT 24 |
Jul 09 05:28:09 PM PDT 24 |
101718700 ps |
| T280 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.1681252819 |
|
|
Jul 09 05:28:00 PM PDT 24 |
Jul 09 05:28:17 PM PDT 24 |
80836300 ps |
| T1121 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.3916571196 |
|
|
Jul 09 05:27:43 PM PDT 24 |
Jul 09 05:27:59 PM PDT 24 |
22094100 ps |
| T230 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.2427013607 |
|
|
Jul 09 05:27:45 PM PDT 24 |
Jul 09 05:35:34 PM PDT 24 |
1864370600 ps |
| T1122 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.1831759405 |
|
|
Jul 09 05:27:43 PM PDT 24 |
Jul 09 05:27:59 PM PDT 24 |
13146200 ps |
| T281 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.908717342 |
|
|
Jul 09 05:27:37 PM PDT 24 |
Jul 09 05:28:18 PM PDT 24 |
1598581600 ps |
| T227 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.540383271 |
|
|
Jul 09 05:27:45 PM PDT 24 |
Jul 09 05:28:06 PM PDT 24 |
120760500 ps |
| T1123 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.756411144 |
|
|
Jul 09 05:28:09 PM PDT 24 |
Jul 09 05:28:28 PM PDT 24 |
206294500 ps |
| T320 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.3322236604 |
|
|
Jul 09 05:28:10 PM PDT 24 |
Jul 09 05:28:25 PM PDT 24 |
25715700 ps |
| T1124 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.4084385281 |
|
|
Jul 09 05:27:42 PM PDT 24 |
Jul 09 05:27:56 PM PDT 24 |
54085800 ps |
| T228 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1097814764 |
|
|
Jul 09 05:27:58 PM PDT 24 |
Jul 09 05:28:17 PM PDT 24 |
97700000 ps |
| T1125 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2145947655 |
|
|
Jul 09 05:27:36 PM PDT 24 |
Jul 09 05:27:52 PM PDT 24 |
18471900 ps |
| T1126 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3690679454 |
|
|
Jul 09 05:27:56 PM PDT 24 |
Jul 09 05:28:12 PM PDT 24 |
14738800 ps |
| T1127 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.617595128 |
|
|
Jul 09 05:27:57 PM PDT 24 |
Jul 09 05:28:12 PM PDT 24 |
67175900 ps |
| T1128 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.2871490605 |
|
|
Jul 09 05:27:52 PM PDT 24 |
Jul 09 05:28:07 PM PDT 24 |
17535300 ps |
| T282 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.745203096 |
|
|
Jul 09 05:27:33 PM PDT 24 |
Jul 09 05:28:18 PM PDT 24 |
1420919400 ps |
| T1129 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.3997674358 |
|
|
Jul 09 05:27:47 PM PDT 24 |
Jul 09 05:28:01 PM PDT 24 |
34434400 ps |
| T1130 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.437048359 |
|
|
Jul 09 05:27:45 PM PDT 24 |
Jul 09 05:28:17 PM PDT 24 |
165018100 ps |
| T321 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.870972538 |
|
|
Jul 09 05:27:44 PM PDT 24 |
Jul 09 05:27:58 PM PDT 24 |
88763800 ps |
| T229 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1986997467 |
|
|
Jul 09 05:27:46 PM PDT 24 |
Jul 09 05:42:58 PM PDT 24 |
3546276700 ps |
| T1131 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.2733048775 |
|
|
Jul 09 05:27:57 PM PDT 24 |
Jul 09 05:28:12 PM PDT 24 |
30061400 ps |
| T235 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.4288532677 |
|
|
Jul 09 05:27:39 PM PDT 24 |
Jul 09 05:27:53 PM PDT 24 |
80965000 ps |
| T283 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1751407195 |
|
|
Jul 09 05:27:56 PM PDT 24 |
Jul 09 05:28:16 PM PDT 24 |
660708800 ps |
| T236 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3283480652 |
|
|
Jul 09 05:27:34 PM PDT 24 |
Jul 09 05:27:50 PM PDT 24 |
16544100 ps |
| T231 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.3969729600 |
|
|
Jul 09 05:27:54 PM PDT 24 |
Jul 09 05:28:15 PM PDT 24 |
52985600 ps |
| T1132 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.2596458635 |
|
|
Jul 09 05:28:04 PM PDT 24 |
Jul 09 05:28:18 PM PDT 24 |
48206300 ps |
| T249 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.1405418135 |
|
|
Jul 09 05:27:32 PM PDT 24 |
Jul 09 05:42:54 PM PDT 24 |
3652630000 ps |
| T250 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.2564172896 |
|
|
Jul 09 05:27:50 PM PDT 24 |
Jul 09 05:28:10 PM PDT 24 |
202996100 ps |
| T1133 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.4062705259 |
|
|
Jul 09 05:27:35 PM PDT 24 |
Jul 09 05:27:53 PM PDT 24 |
301196000 ps |
| T1134 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.1974634814 |
|
|
Jul 09 05:27:46 PM PDT 24 |
Jul 09 05:28:01 PM PDT 24 |
28535400 ps |
| T1135 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.1262690878 |
|
|
Jul 09 05:27:34 PM PDT 24 |
Jul 09 05:27:49 PM PDT 24 |
23313500 ps |
| T1136 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.3542464628 |
|
|
Jul 09 05:27:36 PM PDT 24 |
Jul 09 05:27:51 PM PDT 24 |
29675500 ps |
| T284 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3631565315 |
|
|
Jul 09 05:27:42 PM PDT 24 |
Jul 09 05:28:30 PM PDT 24 |
83826700 ps |
| T1137 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.3362097085 |
|
|
Jul 09 05:27:58 PM PDT 24 |
Jul 09 05:28:13 PM PDT 24 |
16789700 ps |
| T314 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.841171493 |
|
|
Jul 09 05:27:50 PM PDT 24 |
Jul 09 05:28:11 PM PDT 24 |
405573800 ps |
| T252 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.607997741 |
|
|
Jul 09 05:27:45 PM PDT 24 |
Jul 09 05:28:03 PM PDT 24 |
80242100 ps |
| T285 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.4001881317 |
|
|
Jul 09 05:27:37 PM PDT 24 |
Jul 09 05:27:57 PM PDT 24 |
128843500 ps |
| T1138 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3015960003 |
|
|
Jul 09 05:27:46 PM PDT 24 |
Jul 09 05:35:26 PM PDT 24 |
368785000 ps |
| T247 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.4098558950 |
|
|
Jul 09 05:28:08 PM PDT 24 |
Jul 09 05:28:29 PM PDT 24 |
228747800 ps |
| T286 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.994658147 |
|
|
Jul 09 05:27:54 PM PDT 24 |
Jul 09 05:42:55 PM PDT 24 |
2921885900 ps |
| T1139 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2915325364 |
|
|
Jul 09 05:27:54 PM PDT 24 |
Jul 09 05:28:08 PM PDT 24 |
29897200 ps |
| T251 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.1600251744 |
|
|
Jul 09 05:27:35 PM PDT 24 |
Jul 09 05:27:52 PM PDT 24 |
61143300 ps |
| T1140 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.452729345 |
|
|
Jul 09 05:27:37 PM PDT 24 |
Jul 09 05:27:55 PM PDT 24 |
37804000 ps |
| T1141 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.854132156 |
|
|
Jul 09 05:27:44 PM PDT 24 |
Jul 09 05:28:05 PM PDT 24 |
1538383200 ps |
| T337 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1514916801 |
|
|
Jul 09 05:27:46 PM PDT 24 |
Jul 09 05:43:06 PM PDT 24 |
390420100 ps |
| T1142 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.3926804405 |
|
|
Jul 09 05:27:33 PM PDT 24 |
Jul 09 05:27:48 PM PDT 24 |
15663400 ps |
| T1143 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.2246948547 |
|
|
Jul 09 05:27:58 PM PDT 24 |
Jul 09 05:28:12 PM PDT 24 |
48982600 ps |
| T334 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.894200682 |
|
|
Jul 09 05:27:42 PM PDT 24 |
Jul 09 05:28:00 PM PDT 24 |
85897600 ps |
| T1144 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.1441521577 |
|
|
Jul 09 05:27:33 PM PDT 24 |
Jul 09 05:28:20 PM PDT 24 |
296119600 ps |
| T339 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1270083992 |
|
|
Jul 09 05:27:38 PM PDT 24 |
Jul 09 05:42:45 PM PDT 24 |
341256400 ps |
| T1145 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.206526968 |
|
|
Jul 09 05:27:39 PM PDT 24 |
Jul 09 05:27:54 PM PDT 24 |
15321500 ps |
| T1146 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2769354465 |
|
|
Jul 09 05:27:39 PM PDT 24 |
Jul 09 05:27:53 PM PDT 24 |
14392500 ps |
| T253 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.3961237676 |
|
|
Jul 09 05:27:51 PM PDT 24 |
Jul 09 05:28:12 PM PDT 24 |
214999800 ps |
| T1147 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3650291646 |
|
|
Jul 09 05:27:33 PM PDT 24 |
Jul 09 05:28:19 PM PDT 24 |
85352300 ps |
| T344 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.704657633 |
|
|
Jul 09 05:27:46 PM PDT 24 |
Jul 09 05:34:19 PM PDT 24 |
447296800 ps |
| T1148 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.3092709817 |
|
|
Jul 09 05:27:32 PM PDT 24 |
Jul 09 05:29:00 PM PDT 24 |
9372725300 ps |
| T1149 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1632144539 |
|
|
Jul 09 05:27:46 PM PDT 24 |
Jul 09 05:28:03 PM PDT 24 |
23549100 ps |
| T1150 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.2285772476 |
|
|
Jul 09 05:27:54 PM PDT 24 |
Jul 09 05:28:09 PM PDT 24 |
47383800 ps |
| T1151 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.2164474047 |
|
|
Jul 09 05:27:49 PM PDT 24 |
Jul 09 05:28:03 PM PDT 24 |
43199900 ps |
| T1152 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.437456323 |
|
|
Jul 09 05:27:59 PM PDT 24 |
Jul 09 05:28:14 PM PDT 24 |
223688300 ps |
| T1153 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.1852389120 |
|
|
Jul 09 05:28:08 PM PDT 24 |
Jul 09 05:28:25 PM PDT 24 |
144317500 ps |
| T1154 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.3252655982 |
|
|
Jul 09 05:27:45 PM PDT 24 |
Jul 09 05:28:00 PM PDT 24 |
14805500 ps |
| T1155 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.3434280161 |
|
|
Jul 09 05:27:44 PM PDT 24 |
Jul 09 05:28:00 PM PDT 24 |
37418900 ps |
| T1156 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.4102888540 |
|
|
Jul 09 05:27:46 PM PDT 24 |
Jul 09 05:28:00 PM PDT 24 |
158421400 ps |
| T287 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.738103967 |
|
|
Jul 09 05:27:50 PM PDT 24 |
Jul 09 05:28:08 PM PDT 24 |
220575100 ps |
| T1157 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.3498288630 |
|
|
Jul 09 05:27:46 PM PDT 24 |
Jul 09 05:28:00 PM PDT 24 |
46964300 ps |
| T1158 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.2266349452 |
|
|
Jul 09 05:27:47 PM PDT 24 |
Jul 09 05:28:05 PM PDT 24 |
35683800 ps |
| T288 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2635774349 |
|
|
Jul 09 05:27:37 PM PDT 24 |
Jul 09 05:28:14 PM PDT 24 |
335762000 ps |
| T289 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3225328092 |
|
|
Jul 09 05:27:35 PM PDT 24 |
Jul 09 05:28:45 PM PDT 24 |
1786265400 ps |
| T1159 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.4247400312 |
|
|
Jul 09 05:27:58 PM PDT 24 |
Jul 09 05:28:12 PM PDT 24 |
50735700 ps |
| T1160 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.3689564548 |
|
|
Jul 09 05:27:55 PM PDT 24 |
Jul 09 05:28:12 PM PDT 24 |
35044900 ps |
| T1161 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.3532335978 |
|
|
Jul 09 05:27:34 PM PDT 24 |
Jul 09 05:27:49 PM PDT 24 |
57571400 ps |
| T248 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2045525222 |
|
|
Jul 09 05:27:56 PM PDT 24 |
Jul 09 05:28:15 PM PDT 24 |
137634400 ps |
| T1162 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.2924443693 |
|
|
Jul 09 05:27:46 PM PDT 24 |
Jul 09 05:28:04 PM PDT 24 |
41810600 ps |
| T1163 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.930443330 |
|
|
Jul 09 05:27:36 PM PDT 24 |
Jul 09 05:27:55 PM PDT 24 |
66092100 ps |
| T1164 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.3928505854 |
|
|
Jul 09 05:28:06 PM PDT 24 |
Jul 09 05:28:21 PM PDT 24 |
26302900 ps |
| T1165 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.4219007209 |
|
|
Jul 09 05:27:44 PM PDT 24 |
Jul 09 05:28:00 PM PDT 24 |
138837100 ps |
| T1166 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.2874084114 |
|
|
Jul 09 05:27:37 PM PDT 24 |
Jul 09 05:27:58 PM PDT 24 |
310075200 ps |
| T1167 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.1650488555 |
|
|
Jul 09 05:27:34 PM PDT 24 |
Jul 09 05:27:49 PM PDT 24 |
28929600 ps |
| T1168 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.2631500789 |
|
|
Jul 09 05:27:36 PM PDT 24 |
Jul 09 05:27:52 PM PDT 24 |
274411900 ps |
| T335 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.4008991667 |
|
|
Jul 09 05:27:37 PM PDT 24 |
Jul 09 05:27:55 PM PDT 24 |
32958800 ps |
| T1169 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.4263545099 |
|
|
Jul 09 05:27:34 PM PDT 24 |
Jul 09 05:27:51 PM PDT 24 |
21462500 ps |
| T1170 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.1215771420 |
|
|
Jul 09 05:27:44 PM PDT 24 |
Jul 09 05:28:05 PM PDT 24 |
39154100 ps |
| T1171 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1841517086 |
|
|
Jul 09 05:27:44 PM PDT 24 |
Jul 09 05:28:03 PM PDT 24 |
107156700 ps |
| T237 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.924485133 |
|
|
Jul 09 05:27:41 PM PDT 24 |
Jul 09 05:27:56 PM PDT 24 |
32735300 ps |
| T1172 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.92850780 |
|
|
Jul 09 05:27:30 PM PDT 24 |
Jul 09 05:27:48 PM PDT 24 |
28685200 ps |
| T1173 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.3212394453 |
|
|
Jul 09 05:27:54 PM PDT 24 |
Jul 09 05:28:08 PM PDT 24 |
29910600 ps |
| T254 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.3029322798 |
|
|
Jul 09 05:28:02 PM PDT 24 |
Jul 09 05:35:34 PM PDT 24 |
422996000 ps |
| T1174 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.3247557517 |
|
|
Jul 09 05:27:40 PM PDT 24 |
Jul 09 05:27:53 PM PDT 24 |
17586200 ps |
| T340 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.2431521330 |
|
|
Jul 09 05:28:01 PM PDT 24 |
Jul 09 05:40:36 PM PDT 24 |
751193300 ps |
| T1175 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3015158493 |
|
|
Jul 09 05:27:46 PM PDT 24 |
Jul 09 05:28:57 PM PDT 24 |
4604037600 ps |
| T1176 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.4175646464 |
|
|
Jul 09 05:27:40 PM PDT 24 |
Jul 09 05:27:57 PM PDT 24 |
55553100 ps |
| T1177 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.1390553038 |
|
|
Jul 09 05:27:56 PM PDT 24 |
Jul 09 05:28:14 PM PDT 24 |
39247800 ps |
| T1178 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3970474852 |
|
|
Jul 09 05:27:45 PM PDT 24 |
Jul 09 05:27:59 PM PDT 24 |
13111400 ps |
| T1179 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.306537927 |
|
|
Jul 09 05:27:35 PM PDT 24 |
Jul 09 05:28:06 PM PDT 24 |
60311800 ps |
| T1180 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.4105756249 |
|
|
Jul 09 05:27:49 PM PDT 24 |
Jul 09 05:28:05 PM PDT 24 |
13441100 ps |
| T1181 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2002881271 |
|
|
Jul 09 05:28:02 PM PDT 24 |
Jul 09 05:28:18 PM PDT 24 |
21685000 ps |
| T1182 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.4172633031 |
|
|
Jul 09 05:27:47 PM PDT 24 |
Jul 09 05:28:06 PM PDT 24 |
399698000 ps |
| T1183 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1900499106 |
|
|
Jul 09 05:27:52 PM PDT 24 |
Jul 09 05:28:13 PM PDT 24 |
918120700 ps |
| T341 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.3732951289 |
|
|
Jul 09 05:27:43 PM PDT 24 |
Jul 09 05:42:58 PM PDT 24 |
1282164000 ps |
| T1184 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.2618390284 |
|
|
Jul 09 05:27:45 PM PDT 24 |
Jul 09 05:27:59 PM PDT 24 |
12076600 ps |
| T1185 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3472881807 |
|
|
Jul 09 05:27:45 PM PDT 24 |
Jul 09 05:28:17 PM PDT 24 |
28059800 ps |
| T1186 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1602999361 |
|
|
Jul 09 05:27:54 PM PDT 24 |
Jul 09 05:28:10 PM PDT 24 |
150399800 ps |
| T1187 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.1787453709 |
|
|
Jul 09 05:27:58 PM PDT 24 |
Jul 09 05:28:13 PM PDT 24 |
59013200 ps |
| T1188 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.1915735947 |
|
|
Jul 09 05:27:59 PM PDT 24 |
Jul 09 05:28:14 PM PDT 24 |
212976600 ps |
| T1189 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.766768543 |
|
|
Jul 09 05:27:43 PM PDT 24 |
Jul 09 05:28:03 PM PDT 24 |
59807400 ps |
| T1190 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2985895654 |
|
|
Jul 09 05:27:57 PM PDT 24 |
Jul 09 05:28:14 PM PDT 24 |
13005200 ps |
| T1191 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.2173217826 |
|
|
Jul 09 05:27:34 PM PDT 24 |
Jul 09 05:27:49 PM PDT 24 |
52393500 ps |
| T1192 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2993239817 |
|
|
Jul 09 05:27:55 PM PDT 24 |
Jul 09 05:28:12 PM PDT 24 |
13292900 ps |
| T1193 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1157761820 |
|
|
Jul 09 05:27:56 PM PDT 24 |
Jul 09 05:28:15 PM PDT 24 |
91536000 ps |
| T1194 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.1355774735 |
|
|
Jul 09 05:27:53 PM PDT 24 |
Jul 09 05:28:08 PM PDT 24 |
31793900 ps |
| T1195 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.1800503854 |
|
|
Jul 09 05:27:53 PM PDT 24 |
Jul 09 05:28:08 PM PDT 24 |
45851100 ps |
| T1196 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.4200067248 |
|
|
Jul 09 05:27:49 PM PDT 24 |
Jul 09 05:28:07 PM PDT 24 |
91522700 ps |
| T1197 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.2800284354 |
|
|
Jul 09 05:27:56 PM PDT 24 |
Jul 09 05:28:12 PM PDT 24 |
16700300 ps |
| T1198 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.1689977968 |
|
|
Jul 09 05:27:45 PM PDT 24 |
Jul 09 05:28:03 PM PDT 24 |
146739700 ps |
| T1199 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.4135110931 |
|
|
Jul 09 05:27:33 PM PDT 24 |
Jul 09 05:28:36 PM PDT 24 |
6272012200 ps |
| T1200 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.1867568378 |
|
|
Jul 09 05:27:47 PM PDT 24 |
Jul 09 05:28:04 PM PDT 24 |
18664400 ps |
| T345 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.2690575184 |
|
|
Jul 09 05:27:40 PM PDT 24 |
Jul 09 05:34:11 PM PDT 24 |
722238900 ps |
| T1201 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.789131926 |
|
|
Jul 09 05:28:03 PM PDT 24 |
Jul 09 05:28:17 PM PDT 24 |
20846200 ps |
| T1202 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3077855288 |
|
|
Jul 09 05:27:29 PM PDT 24 |
Jul 09 05:27:45 PM PDT 24 |
52080100 ps |
| T1203 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.2580325554 |
|
|
Jul 09 05:27:51 PM PDT 24 |
Jul 09 05:28:09 PM PDT 24 |
101099300 ps |
| T1204 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.1315533274 |
|
|
Jul 09 05:27:58 PM PDT 24 |
Jul 09 05:28:12 PM PDT 24 |
26301700 ps |
| T1205 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1099594225 |
|
|
Jul 09 05:27:39 PM PDT 24 |
Jul 09 05:27:55 PM PDT 24 |
20991500 ps |
| T1206 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.1696262777 |
|
|
Jul 09 05:27:42 PM PDT 24 |
Jul 09 05:28:00 PM PDT 24 |
12544600 ps |
| T1207 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3509044186 |
|
|
Jul 09 05:27:42 PM PDT 24 |
Jul 09 05:28:19 PM PDT 24 |
250662300 ps |
| T1208 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2025932116 |
|
|
Jul 09 05:27:50 PM PDT 24 |
Jul 09 05:28:05 PM PDT 24 |
29459400 ps |
| T1209 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.878674118 |
|
|
Jul 09 05:27:56 PM PDT 24 |
Jul 09 05:28:12 PM PDT 24 |
16863600 ps |
| T1210 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2165639754 |
|
|
Jul 09 05:27:48 PM PDT 24 |
Jul 09 05:28:05 PM PDT 24 |
16673300 ps |
| T1211 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.2321524778 |
|
|
Jul 09 05:27:41 PM PDT 24 |
Jul 09 05:27:58 PM PDT 24 |
69514100 ps |
| T1212 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.446572715 |
|
|
Jul 09 05:28:07 PM PDT 24 |
Jul 09 05:28:27 PM PDT 24 |
163863800 ps |
| T1213 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.3393737924 |
|
|
Jul 09 05:27:44 PM PDT 24 |
Jul 09 05:28:02 PM PDT 24 |
135859800 ps |
| T1214 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1294434731 |
|
|
Jul 09 05:27:55 PM PDT 24 |
Jul 09 05:28:13 PM PDT 24 |
370213800 ps |
| T1215 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.397820808 |
|
|
Jul 09 05:28:09 PM PDT 24 |
Jul 09 05:28:28 PM PDT 24 |
34243500 ps |
| T1216 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1766685515 |
|
|
Jul 09 05:27:42 PM PDT 24 |
Jul 09 05:27:57 PM PDT 24 |
46630500 ps |
| T1217 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.469326579 |
|
|
Jul 09 05:28:09 PM PDT 24 |
Jul 09 05:28:25 PM PDT 24 |
29965000 ps |
| T1218 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.2929818266 |
|
|
Jul 09 05:28:00 PM PDT 24 |
Jul 09 05:28:15 PM PDT 24 |
14527800 ps |
| T1219 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.3977995055 |
|
|
Jul 09 05:27:34 PM PDT 24 |
Jul 09 05:28:27 PM PDT 24 |
454777400 ps |
| T1220 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.993958614 |
|
|
Jul 09 05:27:42 PM PDT 24 |
Jul 09 05:28:00 PM PDT 24 |
37021900 ps |
| T343 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2142217611 |
|
|
Jul 09 05:27:43 PM PDT 24 |
Jul 09 05:35:30 PM PDT 24 |
644799800 ps |
| T1221 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.2822236688 |
|
|
Jul 09 05:28:10 PM PDT 24 |
Jul 09 05:28:25 PM PDT 24 |
92592300 ps |
| T1222 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.3208666335 |
|
|
Jul 09 05:27:48 PM PDT 24 |
Jul 09 05:28:06 PM PDT 24 |
52868100 ps |
| T1223 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2754266888 |
|
|
Jul 09 05:27:55 PM PDT 24 |
Jul 09 05:28:16 PM PDT 24 |
63546700 ps |
| T1224 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.1143279029 |
|
|
Jul 09 05:27:50 PM PDT 24 |
Jul 09 05:28:11 PM PDT 24 |
111687700 ps |
| T1225 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.4070663975 |
|
|
Jul 09 05:27:48 PM PDT 24 |
Jul 09 05:28:05 PM PDT 24 |
44382700 ps |
| T1226 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2250973682 |
|
|
Jul 09 05:27:49 PM PDT 24 |
Jul 09 05:28:11 PM PDT 24 |
279612100 ps |
| T1227 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.1763639771 |
|
|
Jul 09 05:27:37 PM PDT 24 |
Jul 09 05:28:44 PM PDT 24 |
3946534300 ps |
| T1228 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.532363345 |
|
|
Jul 09 05:27:55 PM PDT 24 |
Jul 09 05:28:10 PM PDT 24 |
32636300 ps |
| T1229 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.4039512662 |
|
|
Jul 09 05:27:54 PM PDT 24 |
Jul 09 05:28:08 PM PDT 24 |
15849500 ps |
| T338 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1660212702 |
|
|
Jul 09 05:27:35 PM PDT 24 |
Jul 09 05:35:16 PM PDT 24 |
1330888800 ps |
| T1230 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.4269992253 |
|
|
Jul 09 05:27:34 PM PDT 24 |
Jul 09 05:27:48 PM PDT 24 |
129927800 ps |
| T1231 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.3633278863 |
|
|
Jul 09 05:27:53 PM PDT 24 |
Jul 09 05:28:13 PM PDT 24 |
195867200 ps |
| T1232 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.1132950831 |
|
|
Jul 09 05:27:36 PM PDT 24 |
Jul 09 05:27:52 PM PDT 24 |
133646900 ps |
| T1233 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.471327569 |
|
|
Jul 09 05:28:01 PM PDT 24 |
Jul 09 05:28:21 PM PDT 24 |
42697300 ps |
| T1234 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.4193337032 |
|
|
Jul 09 05:27:44 PM PDT 24 |
Jul 09 05:27:57 PM PDT 24 |
56329600 ps |
| T1235 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.2483043449 |
|
|
Jul 09 05:27:36 PM PDT 24 |
Jul 09 05:27:56 PM PDT 24 |
153191500 ps |
| T1236 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.1199441286 |
|
|
Jul 09 05:27:54 PM PDT 24 |
Jul 09 05:28:11 PM PDT 24 |
78762100 ps |
| T1237 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.2705793159 |
|
|
Jul 09 05:27:58 PM PDT 24 |
Jul 09 05:28:15 PM PDT 24 |
79011300 ps |
| T1238 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.675469831 |
|
|
Jul 09 05:27:45 PM PDT 24 |
Jul 09 05:28:01 PM PDT 24 |
44047300 ps |
| T1239 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.4035890774 |
|
|
Jul 09 05:27:38 PM PDT 24 |
Jul 09 05:27:56 PM PDT 24 |
126875700 ps |
| T1240 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1003774796 |
|
|
Jul 09 05:27:46 PM PDT 24 |
Jul 09 05:28:08 PM PDT 24 |
152422900 ps |
| T1241 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.442452281 |
|
|
Jul 09 05:27:29 PM PDT 24 |
Jul 09 05:27:44 PM PDT 24 |
48346300 ps |
| T1242 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.2600309515 |
|
|
Jul 09 05:27:36 PM PDT 24 |
Jul 09 05:27:53 PM PDT 24 |
96037500 ps |
| T1243 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.2960672416 |
|
|
Jul 09 05:27:34 PM PDT 24 |
Jul 09 05:27:51 PM PDT 24 |
25764800 ps |
| T1244 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.3486563716 |
|
|
Jul 09 05:27:45 PM PDT 24 |
Jul 09 05:28:30 PM PDT 24 |
3459818600 ps |
| T1245 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2306322709 |
|
|
Jul 09 05:27:45 PM PDT 24 |
Jul 09 05:28:04 PM PDT 24 |
274522900 ps |
| T1246 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.186778547 |
|
|
Jul 09 05:27:50 PM PDT 24 |
Jul 09 05:28:07 PM PDT 24 |
14857200 ps |
| T1247 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.14490921 |
|
|
Jul 09 05:27:32 PM PDT 24 |
Jul 09 05:27:49 PM PDT 24 |
17689900 ps |
| T1248 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.3395487335 |
|
|
Jul 09 05:27:53 PM PDT 24 |
Jul 09 05:28:09 PM PDT 24 |
172338100 ps |
| T255 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.1785636233 |
|
|
Jul 09 05:27:37 PM PDT 24 |
Jul 09 05:27:55 PM PDT 24 |
99609000 ps |
| T1249 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.31594377 |
|
|
Jul 09 05:27:52 PM PDT 24 |
Jul 09 05:28:06 PM PDT 24 |
17340900 ps |
| T1250 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.4052395485 |
|
|
Jul 09 05:27:55 PM PDT 24 |
Jul 09 05:28:11 PM PDT 24 |
18361800 ps |
| T342 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3822711358 |
|
|
Jul 09 05:28:01 PM PDT 24 |
Jul 09 05:35:29 PM PDT 24 |
179629500 ps |
| T1251 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.1740042116 |
|
|
Jul 09 05:27:45 PM PDT 24 |
Jul 09 05:28:00 PM PDT 24 |
21561300 ps |