Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	259845	1		T1	2		T2	2		T3	1
all_values[1]	259845	1		T1	2		T2	2		T3	1
all_values[2]	259845	1		T1	2		T2	2		T3	1
all_values[3]	259845	1		T1	2		T2	2		T3	1
all_values[4]	259845	1		T1	2		T2	2		T3	1
all_values[5]	259845	1		T1	2		T2	2		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	525824	1		T1	12		T2	12		T3	6
auto[1]	1033246	1		T21	41568		T26	6212		T27	6684

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	764022	1		T1	7		T2	7		T3	4
auto[1]	795048	1		T1	5		T2	5		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	259686	1		T1	2		T2	2		T3	1
all_values[0]	auto[1]	auto[1]	159	1		T243	3		T244	4		T245	7
all_values[1]	auto[0]	auto[1]	259678	1		T1	2		T2	2		T3	1
all_values[1]	auto[1]	auto[1]	167	1		T243	6		T244	5		T245	3
all_values[2]	auto[0]	auto[0]	1560	1		T1	2		T2	2		T3	1
all_values[2]	auto[0]	auto[1]	59	1		T243	3		T245	1		T317	3
all_values[2]	auto[1]	auto[0]	258176	1		T21	10392		T26	1553		T27	1671
all_values[2]	auto[1]	auto[1]	50	1		T245	2		T318	2		T319	2
all_values[3]	auto[0]	auto[0]	1569	1		T1	2		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	52	1		T243	1		T244	1		T317	1
all_values[3]	auto[1]	auto[0]	89422	1		T21	1732		T26	1553		T27	1671
all_values[3]	auto[1]	auto[1]	168802	1		T21	8660		T34	3464		T35	1634
all_values[4]	auto[0]	auto[0]	1123	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	497	1		T1	1		T2	1		T4	1
all_values[4]	auto[1]	auto[0]	152497	1		T21	8660		T26	1		T27	1
all_values[4]	auto[1]	auto[1]	105728	1		T21	1732		T26	1552		T27	1670
all_values[5]	auto[0]	auto[0]	1502	1		T1	2		T2	2		T3	1
all_values[5]	auto[0]	auto[1]	98	1		T20	1		T36	1		T37	1
all_values[5]	auto[1]	auto[0]	258173	1		T21	10392		T26	1553		T27	1671
all_values[5]	auto[1]	auto[1]	72	1		T245	2		T317	3		T318	1