Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	259639	1		T1	1484		T2	1		T4	100
auto[FlashEraseBank]	279463	1		T1	1799		T4	1197		T9	10

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	259008	1		T1	1254		T4	670		T9	26
auto[FlashOpProgram]	259768	1		T1	2029		T4	579		T8	2089
auto[FlashOpErase]	16326	1		T2	1		T4	48		T9	16
auto[FlashOpInvalid]	4000	1		T83	200		T132	200		T279	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	259008	1		T1	1254		T4	670		T9	26
op[FlashOpProgram]	259768	1		T1	2029		T4	579		T8	2089
op[FlashOpErase]	16326	1		T2	1		T4	48		T9	16
read_erase_read	565	1		T4	7		T9	10		T29	2
read_prog_read	911	1		T1	6		T4	4		T8	6

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	396338	1		T1	2761		T4	98		T9	17
auto[FlashPartInfo]	139044	1		T1	506		T2	1		T4	1198
auto[FlashPartInfo1]	858	1		T1	2		T8	2		T119	2
auto[FlashPartInfo2]	2862	1		T1	14		T4	1		T8	10

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	188105	1		T1	883		T4	29		T9	8
auto[FlashPartData]	auto[FlashOpProgram]	200719	1		T1	1878		T4	35		T8	1871
auto[FlashPartData]	auto[FlashOpErase]	3602	1		T4	34		T9	9		T40	2
auto[FlashPartData]	auto[FlashOpInvalid]	3912	1		T83	198		T132	196		T279	198
auto[FlashPartInfo]	auto[FlashOpRead]	68355	1		T1	365		T4	641		T9	18
auto[FlashPartInfo]	auto[FlashOpProgram]	57935	1		T1	141		T4	544		T8	216
auto[FlashPartInfo]	auto[FlashOpErase]	12678	1		T2	1		T4	13		T9	7
auto[FlashPartInfo]	auto[FlashOpInvalid]	76	1		T83	2		T132	4		T279	2
auto[FlashPartInfo1]	auto[FlashOpRead]	683	1		T1	2		T8	2		T119	2
auto[FlashPartInfo1]	auto[FlashOpProgram]	166	1		T122	1		T124	1		T125	1
auto[FlashPartInfo1]	auto[FlashOpErase]	3	1		T124	1		T375	1		T376	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	6	1		T124	2		T375	2		T376	2
auto[FlashPartInfo2]	auto[FlashOpRead]	1865	1		T1	4		T8	8		T5	1
auto[FlashPartInfo2]	auto[FlashOpProgram]	948	1		T1	10		T8	2		T20	3
auto[FlashPartInfo2]	auto[FlashOpErase]	43	1		T4	1		T133	2		T143	6
auto[FlashPartInfo2]	auto[FlashOpInvalid]	6	1		T377	2		T378	2		T379	2