Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	32184	1		T4	28		T6	580		T44	636
auto[1]	56	1		T5	1		T133	2		T198	11
auto[2]	53	1		T129	1		T73	4		T72	8
auto[3]	219	1		T9	16		T8	1		T24	1

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	8132	1		T4	7		T9	4		T6	145
evic_idx[1]	8127	1		T4	7		T9	4		T6	145
evic_idx[2]	8131	1		T4	7		T9	5		T6	145
evic_idx[3]	8122	1		T4	7		T9	3		T8	1

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	31495	1		T9	16		T6	580		T44	636
evic_op[2]	356	1		T8	1		T5	1		T29	4

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7814	1		T6	145		T44	159		T47	77
evic_idx[0]	evic_op[1]	auto[1]	12	1		T198	3		T380	2		T381	3
evic_idx[0]	evic_op[1]	auto[2]	4	1		T133	1		T381	1		T382	1
evic_idx[0]	evic_op[1]	auto[3]	47	1		T9	4		T84	4		T133	1
evic_idx[0]	evic_op[2]	auto[0]	73	1		T29	1		T204	1		T209	1
evic_idx[0]	evic_op[2]	auto[1]	2	1		T86	1		T261	1		-	-
evic_idx[0]	evic_op[2]	auto[2]	4	1		T383	1		T384	1		T385	1
evic_idx[0]	evic_op[2]	auto[3]	10	1		T119	1		T386	1		T383	1
evic_idx[1]	evic_op[1]	auto[0]	7815	1		T6	145		T44	159		T47	77
evic_idx[1]	evic_op[1]	auto[1]	9	1		T133	1		T198	2		T380	1
evic_idx[1]	evic_op[1]	auto[2]	4	1		T381	2		T387	2		-	-
evic_idx[1]	evic_op[1]	auto[3]	46	1		T9	4		T84	2		T143	6
evic_idx[1]	evic_op[2]	auto[0]	70	1		T29	1		T209	1		T122	1
evic_idx[1]	evic_op[2]	auto[1]	4	1		T86	1		T261	1		T388	1
evic_idx[1]	evic_op[2]	auto[2]	5	1		T389	1		T390	1		T383	1
evic_idx[1]	evic_op[2]	auto[3]	9	1		T24	1		T119	1		T265	1
evic_idx[2]	evic_op[1]	auto[0]	7813	1		T6	145		T44	159		T47	77
evic_idx[2]	evic_op[1]	auto[1]	10	1		T133	1		T198	3		T380	2
evic_idx[2]	evic_op[1]	auto[2]	5	1		T391	1		T381	2		T387	2
evic_idx[2]	evic_op[1]	auto[3]	47	1		T9	5		T84	1		T143	6
evic_idx[2]	evic_op[2]	auto[0]	75	1		T29	1		T209	1		T122	1
evic_idx[2]	evic_op[2]	auto[1]	6	1		T86	1		T390	1		T261	1
evic_idx[2]	evic_op[2]	auto[2]	2	1		T129	1		T390	1		-	-
evic_idx[2]	evic_op[2]	auto[3]	8	1		T119	1		T392	1		T393	1
evic_idx[3]	evic_op[1]	auto[0]	7815	1		T6	145		T44	159		T47	77
evic_idx[3]	evic_op[1]	auto[1]	9	1		T198	3		T380	1		T381	3
evic_idx[3]	evic_op[1]	auto[2]	4	1		T133	1		T381	1		T387	1
evic_idx[3]	evic_op[1]	auto[3]	41	1		T9	3		T84	3		T133	2
evic_idx[3]	evic_op[2]	auto[0]	68	1		T29	1		T209	1		T122	1
evic_idx[3]	evic_op[2]	auto[1]	4	1		T5	1		T261	1		T394	1
evic_idx[3]	evic_op[2]	auto[2]	5	1		T384	4		T395	1		-	-
evic_idx[3]	evic_op[2]	auto[3]	11	1		T8	1		T25	1		T119	1