Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
77.78	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	4	14	77.78

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	1	14	93.33	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	1	14	93.33

User Defined Bins for rd_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
rd_lvl[1]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[2]	25817	1		T197	1050		T305	12050		T306	1271
rd_lvl[3]	8445	1		T21	4377		T197	278		T305	539
rd_lvl[4]	24606	1		T21	4283		T207	1401		T197	34
rd_lvl[5]	17797	1		T207	536		T197	224		T307	2163
rd_lvl[6]	18174	1		T207	1		T197	142		T307	1185
rd_lvl[7]	14244	1		T34	1882		T207	63		T197	16
rd_lvl[8]	18709	1		T34	1582		T197	16		T308	1092
rd_lvl[9]	3555	1		T197	16		T309	63		T310	537
rd_lvl[10]	6303	1		T197	4		T309	24		T311	183
rd_lvl[11]	4464	1		T197	2		T311	1415		T31	222
rd_lvl[12]	6711	1		T35	214		T207	63		T197	91
rd_lvl[13]	3360	1		T35	1420		T197	91		T312	112
rd_lvl[14]	2325	1		T313	213		T314	24		T315	281
rd_lvl[15]	3894	1		T32	220		T33	174		T316	582