Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	259845	1		T1	2		T2	2		T3	1
all_pins[1]	259845	1		T1	2		T2	2		T3	1
all_pins[2]	259845	1		T1	2		T2	2		T3	1
all_pins[3]	259845	1		T1	2		T2	2		T3	1
all_pins[4]	259845	1		T1	2		T2	2		T3	1
all_pins[5]	259845	1		T1	2		T2	2		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1275652	1		T1	12		T2	12		T3	6
values[0x1]	283418	1		T21	11616		T26	1552		T27	1670
transitions[0x0=>0x1]	253326	1		T21	10392		T26	1552		T27	1670
transitions[0x1=>0x0]	253307	1		T21	10392		T26	1552		T27	1670

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	259686	1		T1	2		T2	2		T3	1
all_pins[0]	values[0x1]	159	1		T243	3		T244	4		T245	7
all_pins[0]	transitions[0x0=>0x1]	66	1		T245	4		T317	2		T318	2
all_pins[0]	transitions[0x1=>0x0]	74	1		T243	3		T244	1		T317	4
all_pins[1]	values[0x0]	259678	1		T1	2		T2	2		T3	1
all_pins[1]	values[0x1]	167	1		T243	6		T244	5		T245	3
all_pins[1]	transitions[0x0=>0x1]	147	1		T243	6		T244	5		T245	2
all_pins[1]	transitions[0x1=>0x0]	4675	1		T32	1075		T33	283		T316	1208
all_pins[2]	values[0x0]	255150	1		T1	2		T2	2		T3	1
all_pins[2]	values[0x1]	4695	1		T32	1075		T33	283		T316	1208
all_pins[2]	transitions[0x0=>0x1]	40	1		T245	2		T318	1		T319	1
all_pins[2]	transitions[0x1=>0x0]	158884	1		T21	8660		T34	3464		T35	1634
all_pins[3]	values[0x0]	96306	1		T1	2		T2	2		T3	1
all_pins[3]	values[0x1]	163539	1		T21	8660		T34	3464		T35	1634
all_pins[3]	transitions[0x0=>0x1]	138268	1		T21	7436		T34	3464		T35	1634
all_pins[3]	transitions[0x1=>0x0]	89515	1		T21	1732		T26	1552		T27	1670
all_pins[4]	values[0x0]	145059	1		T1	2		T2	2		T3	1
all_pins[4]	values[0x1]	114786	1		T21	2956		T26	1552		T27	1670
all_pins[4]	transitions[0x0=>0x1]	114770	1		T21	2956		T26	1552		T27	1670
all_pins[4]	transitions[0x1=>0x0]	56	1		T317	3		T318	1		T319	3
all_pins[5]	values[0x0]	259773	1		T1	2		T2	2		T3	1
all_pins[5]	values[0x1]	72	1		T245	2		T317	3		T318	1
all_pins[5]	transitions[0x0=>0x1]	35	1		T317	1		T319	2		T321	2
all_pins[5]	transitions[0x1=>0x0]	103	1		T243	3		T244	3		T245	4