Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::sw_error_cg
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Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::sw_error_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
85.71 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv



Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::sw_error_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 7 1 6 85.71


Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::sw_error_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mp_err 1 0 1 100.00 100 1 1 0
cp_op_err 1 0 1 100.00 100 1 1 0
cp_prog_err 1 0 1 100.00 100 1 1 0
cp_prog_type_err 1 0 1 100.00 100 1 1 0
cp_prog_win_err 1 0 1 100.00 100 1 1 0
cp_rd_err 1 0 1 100.00 100 1 1 0
cp_update_err 1 1 0 0.00 100 1 1 0


Summary for Variable cp_mp_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mp_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
seen 251093 1 T1 14379 T42 10 T260 1



Summary for Variable cp_op_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_op_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
seen 4000 1 T83 200 T132 200 T279 200



Summary for Variable cp_prog_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_prog_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
seen 15 1 T10 5 T12 5 T235 5



Summary for Variable cp_prog_type_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_prog_type_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
seen 537 1 T59 90 T88 72 T89 130



Summary for Variable cp_prog_win_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_prog_win_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
seen 290 1 T42 10 T183 10 T233 17



Summary for Variable cp_rd_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_rd_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
seen 138074 1 T1 4079 T5 1 T24 1



Summary for Variable cp_update_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for cp_update_err

Uncovered bins
NAMECOUNTAT LEASTNUMBER
seen 0 1 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%