Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	289302	1		T1	1		T2	2		T3	1
all_values[1]	289302	1		T1	1		T2	2		T3	1
all_values[2]	289302	1		T1	1		T2	2		T3	1
all_values[3]	289302	1		T1	1		T2	2		T3	1
all_values[4]	289302	1		T1	1		T2	2		T3	1
all_values[5]	289302	1		T1	1		T2	2		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	584884	1		T1	6		T2	12		T3	6
auto[1]	1150928	1		T26	5356		T36	12832		T38	19908

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	855147	1		T1	4		T2	7		T3	4
auto[1]	880665	1		T1	2		T2	5		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	289162	1		T1	1		T2	2		T3	1
all_values[0]	auto[1]	auto[1]	140	1		T259	4		T260	4		T325	2
all_values[1]	auto[0]	auto[1]	289121	1		T1	1		T2	2		T3	1
all_values[1]	auto[1]	auto[1]	181	1		T258	3		T259	3		T260	5
all_values[2]	auto[0]	auto[0]	1586	1		T1	1		T2	2		T3	1
all_values[2]	auto[0]	auto[1]	64	1		T258	2		T259	1		T325	3
all_values[2]	auto[1]	auto[0]	287612	1		T26	1339		T36	3208		T38	4977
all_values[2]	auto[1]	auto[1]	40	1		T259	2		T326	2		T343	1
all_values[3]	auto[0]	auto[0]	1588	1		T1	1		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	54	1		T258	3		T259	1		T325	3
all_values[3]	auto[1]	auto[0]	85915	1		T26	327		T36	1604		T38	1659
all_values[3]	auto[1]	auto[1]	201745	1		T26	1012		T36	1604		T38	3318
all_values[4]	auto[0]	auto[0]	1129	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	523	1		T2	1		T6	1		T7	1
all_values[4]	auto[1]	auto[0]	188190	1		T26	833		T36	1604		T38	3318
all_values[4]	auto[1]	auto[1]	99460	1		T26	506		T36	1604		T38	1659
all_values[5]	auto[0]	auto[0]	1545	1		T1	1		T2	2		T3	1
all_values[5]	auto[0]	auto[1]	112	1		T39	1		T40	1		T41	1
all_values[5]	auto[1]	auto[0]	287582	1		T26	1339		T36	3208		T38	4977
all_values[5]	auto[1]	auto[1]	63	1		T258	1		T259	3		T260	1