Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	242170	1		T1	35		T2	5		T4	1483
auto[FlashEraseBank]	271565	1		T1	15		T2	4		T6	564

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	250112	1		T1	32		T2	3		T4	757
auto[FlashOpProgram]	244823	1		T2	4		T4	363		T7	4
auto[FlashOpErase]	14800	1		T1	18		T2	2		T4	363
auto[FlashOpInvalid]	4000	1		T68	200		T162	200		T285	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	250112	1		T1	32		T2	3		T4	757
op[FlashOpProgram]	244823	1		T2	4		T4	363		T7	4
op[FlashOpErase]	14800	1		T1	18		T2	2		T4	363
read_erase_read	586	1		T1	13		T20	2		T37	7
read_prog_read	855	1		T16	3		T18	7		T23	3

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	372759	1		T1	20		T2	9		T6	792
auto[FlashPartInfo]	137538	1		T1	29		T4	1483		T6	262
auto[FlashPartInfo1]	745	1		T6	3		T16	2		T46	1
auto[FlashPartInfo2]	2693	1		T1	1		T6	13		T16	24

---

Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	177957	1		T1	10		T2	3		T6	792
auto[FlashPartData]	auto[FlashOpProgram]	187259	1		T2	4		T7	4		T16	1965
auto[FlashPartData]	auto[FlashOpErase]	3603	1		T1	10		T2	2		T7	10
auto[FlashPartData]	auto[FlashOpInvalid]	3940	1		T68	198		T162	200		T285	198
auto[FlashPartInfo]	auto[FlashOpRead]	69814	1		T1	21		T4	757		T6	262
auto[FlashPartInfo]	auto[FlashOpProgram]	56517	1		T4	363		T16	237		T23	3
auto[FlashPartInfo]	auto[FlashOpErase]	11157	1		T1	8		T4	363		T7	1
auto[FlashPartInfo]	auto[FlashOpInvalid]	50	1		T68	2		T285	2		T407	2
auto[FlashPartInfo1]	auto[FlashOpRead]	570	1		T6	3		T16	2		T46	1
auto[FlashPartInfo1]	auto[FlashOpProgram]	163	1		T150	32		T129	1		T153	1
auto[FlashPartInfo1]	auto[FlashOpErase]	6	1		T31	1		T129	1		T130	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	6	1		T129	2		T153	2		T408	2
auto[FlashPartInfo2]	auto[FlashOpRead]	1771	1		T1	1		T6	13		T16	11
auto[FlashPartInfo2]	auto[FlashOpProgram]	884	1		T16	13		T39	2		T69	16
auto[FlashPartInfo2]	auto[FlashOpErase]	34	1		T74	1		T124	2		T147	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	4	1		T153	2		T409	2		-	-