Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.62	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	1	31	96.88

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	1	31	96.88	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	28920	1		T2	4		T4	696		T7	9
auto[1]	18	1		T1	5		T208	1		T347	1
auto[2]	76	1		T1	9		T21	4		T124	8
auto[3]	213	1		T1	12		T16	3		T23	1

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7312	1		T1	6		T2	1		T4	174
evic_idx[1]	7320	1		T1	7		T2	1		T4	174
evic_idx[2]	7297	1		T1	8		T2	1		T4	174
evic_idx[3]	7298	1		T1	5		T2	1		T4	174

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	28417	1		T1	26		T4	696		T68	400
evic_op[2]	302	1		T7	1		T16	3		T18	32

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	1	31	96.88	1

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[1]]	[evic_op[1]]	[auto[1]]	0	1	1

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7052	1		T4	174		T68	100		T20	4
evic_idx[0]	evic_op[1]	auto[1]	1	1		T1	1		-	-		-	-
evic_idx[0]	evic_op[1]	auto[2]	9	1		T1	2		T21	1		T347	1
evic_idx[0]	evic_op[1]	auto[3]	45	1		T1	3		T21	3		T149	1
evic_idx[0]	evic_op[2]	auto[0]	61	1		T7	1		T18	8		T20	4
evic_idx[0]	evic_op[2]	auto[1]	2	1		T348	1		T349	1		-	-
evic_idx[0]	evic_op[2]	auto[2]	5	1		T350	1		T351	1		T352	1
evic_idx[0]	evic_op[2]	auto[3]	10	1		T203	1		T141	1		T353	1
evic_idx[1]	evic_op[1]	auto[0]	7053	1		T4	174		T68	100		T20	4
evic_idx[1]	evic_op[1]	auto[2]	11	1		T1	4		T21	1		T149	1
evic_idx[1]	evic_op[1]	auto[3]	48	1		T1	3		T21	4		T149	3
evic_idx[1]	evic_op[2]	auto[0]	58	1		T18	8		T20	4		T219	2
evic_idx[1]	evic_op[2]	auto[1]	2	1		T354	1		T348	1		-	-
evic_idx[1]	evic_op[2]	auto[2]	3	1		T43	1		T306	1		T355	1
evic_idx[1]	evic_op[2]	auto[3]	18	1		T16	1		T23	1		T356	1
evic_idx[2]	evic_op[1]	auto[0]	7049	1		T4	174		T68	100		T20	4
evic_idx[2]	evic_op[1]	auto[1]	2	1		T1	2		-	-		-	-
evic_idx[2]	evic_op[1]	auto[2]	9	1		T1	2		T21	1		T347	1
evic_idx[2]	evic_op[1]	auto[3]	37	1		T1	4		T21	4		T149	2
evic_idx[2]	evic_op[2]	auto[0]	60	1		T18	8		T19	1		T20	4
evic_idx[2]	evic_op[2]	auto[1]	3	1		T350	1		T357	1		T348	1
evic_idx[2]	evic_op[2]	auto[2]	2	1		T306	1		T352	1		-	-
evic_idx[2]	evic_op[2]	auto[3]	8	1		T16	1		T43	1		T358	1
evic_idx[3]	evic_op[1]	auto[0]	7052	1		T4	174		T68	100		T20	4
evic_idx[3]	evic_op[1]	auto[1]	3	1		T1	2		T347	1		-	-
evic_idx[3]	evic_op[1]	auto[2]	7	1		T1	1		T21	1		T347	1
evic_idx[3]	evic_op[1]	auto[3]	39	1		T1	2		T21	2		T149	3
evic_idx[3]	evic_op[2]	auto[0]	55	1		T18	8		T20	4		T219	2
evic_idx[3]	evic_op[2]	auto[1]	5	1		T208	1		T359	1		T357	1
evic_idx[3]	evic_op[2]	auto[2]	2	1		T43	1		T352	1		-	-
evic_idx[3]	evic_op[2]	auto[3]	8	1		T16	1		T27	1		T360	1