Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	29111	1		T331	15722		T332	13389		-	-
rd_lvl[2]	37807	1		T333	11898		T334	1102		T331	11350
rd_lvl[3]	4488	1		T333	443		T334	408		T335	1695
rd_lvl[4]	7830	1		T334	69		T336	6477		T335	174
rd_lvl[5]	10287	1		T92	2385		T315	533		T334	373
rd_lvl[6]	15401	1		T26	492		T92	2652		T125	2494
rd_lvl[7]	12615	1		T26	107		T38	1813		T125	632
rd_lvl[8]	12926	1		T26	1		T38	1505		T337	45
rd_lvl[9]	3762	1		T26	178		T337	1		T338	317
rd_lvl[10]	6850	1		T26	179		T25	248		T35	218
rd_lvl[11]	4856	1		T36	207		T25	195		T164	592
rd_lvl[12]	10402	1		T36	1397		T164	960		T338	44
rd_lvl[13]	3409	1		T25	134		T34	72		T121	624
rd_lvl[14]	6958	1		T34	17		T121	923		T339	1046
rd_lvl[15]	2688	1		T340	324		T341	1		T342	180