Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	289302	1		T1	1		T2	2		T3	1
all_pins[1]	289302	1		T1	1		T2	2		T3	1
all_pins[2]	289302	1		T1	1		T2	2		T3	1
all_pins[3]	289302	1		T1	1		T2	2		T3	1
all_pins[4]	289302	1		T1	1		T2	2		T3	1
all_pins[5]	289302	1		T1	1		T2	2		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1457819	1		T1	6		T2	12		T3	6
values[0x1]	277993	1		T26	1463		T36	3208		T38	4977
transitions[0x0=>0x1]	257698	1		T26	1284		T36	3208		T38	4977
transitions[0x1=>0x0]	257690	1		T26	1284		T36	3208		T38	4977

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	289162	1		T1	1		T2	2		T3	1
all_pins[0]	values[0x1]	140	1		T259	4		T260	4		T325	2
all_pins[0]	transitions[0x0=>0x1]	49	1		T259	2		T325	1		T326	1
all_pins[0]	transitions[0x1=>0x0]	90	1		T258	3		T259	1		T260	1
all_pins[1]	values[0x0]	289121	1		T1	1		T2	2		T3	1
all_pins[1]	values[0x1]	181	1		T258	3		T259	3		T260	5
all_pins[1]	transitions[0x0=>0x1]	161	1		T258	3		T259	2		T260	5
all_pins[1]	transitions[0x1=>0x0]	1776	1		T340	305		T94	1		T361	165
all_pins[2]	values[0x0]	287506	1		T1	1		T2	2		T3	1
all_pins[2]	values[0x1]	1796	1		T340	305		T94	1		T361	165
all_pins[2]	transitions[0x0=>0x1]	34	1		T259	1		T326	2		T343	1
all_pins[2]	transitions[0x1=>0x0]	169617	1		T26	957		T36	1604		T38	3318
all_pins[3]	values[0x0]	117923	1		T1	1		T2	2		T3	1
all_pins[3]	values[0x1]	171379	1		T26	957		T36	1604		T38	3318
all_pins[3]	transitions[0x0=>0x1]	153012	1		T26	778		T36	1604		T38	3318
all_pins[3]	transitions[0x1=>0x0]	86067	1		T26	327		T36	1604		T38	1659
all_pins[4]	values[0x0]	184868	1		T1	1		T2	2		T3	1
all_pins[4]	values[0x1]	104434	1		T26	506		T36	1604		T38	1659
all_pins[4]	transitions[0x0=>0x1]	104417	1		T26	506		T36	1604		T38	1659
all_pins[4]	transitions[0x1=>0x0]	46	1		T258	1		T259	2		T260	1
all_pins[5]	values[0x0]	289239	1		T1	1		T2	2		T3	1
all_pins[5]	values[0x1]	63	1		T258	1		T259	3		T260	1
all_pins[5]	transitions[0x0=>0x1]	25	1		T259	2		T325	2		T362	1
all_pins[5]	transitions[0x1=>0x0]	94	1		T259	2		T260	3		T325	2