Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	275	1		T258	4		T259	7		T260	4
all_values[1]	275	1		T258	4		T259	7		T260	4
all_values[2]	275	1		T258	4		T259	7		T260	4
all_values[3]	275	1		T258	4		T259	7		T260	4
all_values[4]	275	1		T258	4		T259	7		T260	4
all_values[5]	275	1		T258	4		T259	7		T260	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	880	1		T258	21		T259	19		T260	14
auto[1]	770	1		T258	3		T259	23		T260	10

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	526	1		T258	9		T259	13		T260	9
auto[1]	1124	1		T258	15		T259	29		T260	15

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	950	1		T258	13		T259	26		T260	19
auto[1]	700	1		T258	11		T259	16		T260	5

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	91	1		T258	2		T259	3		T325	4
all_values[0]	auto[0]	auto[1]	auto[1]	55	1		T259	3		T260	3		T326	5
all_values[0]	auto[1]	auto[0]	auto[1]	77	1		T258	2		T325	2		T326	1
all_values[0]	auto[1]	auto[1]	auto[1]	52	1		T259	1		T260	1		T325	1
all_values[1]	auto[0]	auto[0]	auto[1]	77	1		T259	3		T325	4		T327	2
all_values[1]	auto[0]	auto[1]	auto[1]	91	1		T258	1		T259	2		T260	3
all_values[1]	auto[1]	auto[0]	auto[1]	49	1		T258	2		T325	3		T326	2
all_values[1]	auto[1]	auto[1]	auto[1]	58	1		T258	1		T259	2		T260	1
all_values[2]	auto[0]	auto[0]	auto[0]	97	1		T258	2		T259	2		T260	4
all_values[2]	auto[0]	auto[1]	auto[0]	74	1		T259	2		T325	1		T326	1
all_values[2]	auto[1]	auto[0]	auto[1]	52	1		T258	2		T259	1		T325	1
all_values[2]	auto[1]	auto[1]	auto[1]	52	1		T259	2		T325	2		T326	4
all_values[3]	auto[0]	auto[0]	auto[0]	79	1		T258	1		T259	2		T260	4
all_values[3]	auto[0]	auto[1]	auto[0]	80	1		T259	3		T325	1		T326	2
all_values[3]	auto[1]	auto[0]	auto[1]	65	1		T258	3		T325	3		T326	2
all_values[3]	auto[1]	auto[1]	auto[1]	51	1		T259	2		T325	2		T326	2
all_values[4]	auto[0]	auto[0]	auto[0]	59	1		T258	3		T259	2		T260	1
all_values[4]	auto[0]	auto[0]	auto[1]	30	1		T259	1		T260	2		T327	1
all_values[4]	auto[0]	auto[1]	auto[0]	47	1		T258	1		T259	1		T326	2
all_values[4]	auto[0]	auto[1]	auto[1]	28	1		T328	1		T329	2		T330	1
all_values[4]	auto[1]	auto[0]	auto[1]	55	1		T259	2		T260	1		T325	1
all_values[4]	auto[1]	auto[1]	auto[1]	56	1		T259	1		T325	4		T326	1
all_values[5]	auto[0]	auto[0]	auto[0]	45	1		T258	2		T259	1		T325	1
all_values[5]	auto[0]	auto[0]	auto[1]	28	1		T258	1		T260	1		T325	1
all_values[5]	auto[0]	auto[1]	auto[0]	45	1		T326	1		T328	2		T329	2
all_values[5]	auto[0]	auto[1]	auto[1]	24	1		T259	1		T260	1		T325	1
all_values[5]	auto[1]	auto[0]	auto[1]	76	1		T258	1		T259	2		T260	1
all_values[5]	auto[1]	auto[1]	auto[1]	57	1		T259	3		T260	1		T325	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal