| T1079 |
/workspace/coverage/default/34.flash_ctrl_rw_evict_all_en.3170270468 |
|
|
Jul 11 06:17:13 PM PDT 24 |
Jul 11 06:17:43 PM PDT 24 |
30299200 ps |
| T1080 |
/workspace/coverage/default/38.flash_ctrl_smoke.143190696 |
|
|
Jul 11 06:17:23 PM PDT 24 |
Jul 11 06:19:47 PM PDT 24 |
64714600 ps |
| T1081 |
/workspace/coverage/default/19.flash_ctrl_disable.992991731 |
|
|
Jul 11 06:15:45 PM PDT 24 |
Jul 11 06:16:08 PM PDT 24 |
46112200 ps |
| T1082 |
/workspace/coverage/default/8.flash_ctrl_error_prog_win.4086174027 |
|
|
Jul 11 06:13:13 PM PDT 24 |
Jul 11 06:28:19 PM PDT 24 |
1674689200 ps |
| T1083 |
/workspace/coverage/default/3.flash_ctrl_disable.761347232 |
|
|
Jul 11 06:12:05 PM PDT 24 |
Jul 11 06:12:28 PM PDT 24 |
11018100 ps |
| T1084 |
/workspace/coverage/default/31.flash_ctrl_otp_reset.3811326235 |
|
|
Jul 11 06:16:57 PM PDT 24 |
Jul 11 06:18:48 PM PDT 24 |
109225800 ps |
| T1085 |
/workspace/coverage/default/3.flash_ctrl_serr_address.2154606447 |
|
|
Jul 11 06:12:00 PM PDT 24 |
Jul 11 06:13:42 PM PDT 24 |
3619771000 ps |
| T1086 |
/workspace/coverage/default/7.flash_ctrl_smoke.3409821417 |
|
|
Jul 11 06:12:53 PM PDT 24 |
Jul 11 06:15:47 PM PDT 24 |
76868800 ps |
| T1087 |
/workspace/coverage/default/16.flash_ctrl_ro.3648199018 |
|
|
Jul 11 06:15:10 PM PDT 24 |
Jul 11 06:16:59 PM PDT 24 |
3831762200 ps |
| T1088 |
/workspace/coverage/default/19.flash_ctrl_hw_sec_otp.409120309 |
|
|
Jul 11 06:15:48 PM PDT 24 |
Jul 11 06:18:34 PM PDT 24 |
7840901900 ps |
| T202 |
/workspace/coverage/default/1.flash_ctrl_phy_ack_consistency.3833403868 |
|
|
Jul 11 06:11:43 PM PDT 24 |
Jul 11 06:12:04 PM PDT 24 |
43796600 ps |
| T1089 |
/workspace/coverage/default/14.flash_ctrl_lcmgr_intg.1079470994 |
|
|
Jul 11 06:14:57 PM PDT 24 |
Jul 11 06:15:11 PM PDT 24 |
17079600 ps |
| T1090 |
/workspace/coverage/default/44.flash_ctrl_connect.4188345623 |
|
|
Jul 11 06:17:51 PM PDT 24 |
Jul 11 06:18:08 PM PDT 24 |
23693300 ps |
| T1091 |
/workspace/coverage/default/22.flash_ctrl_sec_info_access.1062038545 |
|
|
Jul 11 06:16:06 PM PDT 24 |
Jul 11 06:17:03 PM PDT 24 |
461639600 ps |
| T1092 |
/workspace/coverage/default/13.flash_ctrl_mp_regions.3744227429 |
|
|
Jul 11 06:14:29 PM PDT 24 |
Jul 11 06:16:50 PM PDT 24 |
14180173500 ps |
| T1093 |
/workspace/coverage/default/29.flash_ctrl_sec_info_access.2011853953 |
|
|
Jul 11 06:16:47 PM PDT 24 |
Jul 11 06:18:01 PM PDT 24 |
1134699000 ps |
| T1094 |
/workspace/coverage/default/3.flash_ctrl_rand_ops.3832471007 |
|
|
Jul 11 06:11:52 PM PDT 24 |
Jul 11 06:18:29 PM PDT 24 |
60925200 ps |
| T1095 |
/workspace/coverage/default/6.flash_ctrl_wo.529581414 |
|
|
Jul 11 06:12:45 PM PDT 24 |
Jul 11 06:16:28 PM PDT 24 |
26180307000 ps |
| T1096 |
/workspace/coverage/default/45.flash_ctrl_hw_sec_otp.2791285407 |
|
|
Jul 11 06:17:53 PM PDT 24 |
Jul 11 06:22:10 PM PDT 24 |
3218101000 ps |
| T211 |
/workspace/coverage/default/0.flash_ctrl_ro_derr.1092176055 |
|
|
Jul 11 06:11:32 PM PDT 24 |
Jul 11 06:14:26 PM PDT 24 |
6592900200 ps |
| T1097 |
/workspace/coverage/default/17.flash_ctrl_prog_reset.462727309 |
|
|
Jul 11 06:15:25 PM PDT 24 |
Jul 11 06:15:40 PM PDT 24 |
20271000 ps |
| T1098 |
/workspace/coverage/default/47.flash_ctrl_alert_test.3424617352 |
|
|
Jul 11 06:17:58 PM PDT 24 |
Jul 11 06:18:13 PM PDT 24 |
161976500 ps |
| T1099 |
/workspace/coverage/default/7.flash_ctrl_error_prog_win.1822311236 |
|
|
Jul 11 06:12:59 PM PDT 24 |
Jul 11 06:28:08 PM PDT 24 |
820009300 ps |
| T1100 |
/workspace/coverage/default/25.flash_ctrl_otp_reset.1199319121 |
|
|
Jul 11 06:16:27 PM PDT 24 |
Jul 11 06:18:39 PM PDT 24 |
40764900 ps |
| T1101 |
/workspace/coverage/default/15.flash_ctrl_ro.1147904549 |
|
|
Jul 11 06:14:55 PM PDT 24 |
Jul 11 06:17:19 PM PDT 24 |
2469917300 ps |
| T1102 |
/workspace/coverage/default/16.flash_ctrl_mp_regions.2878608274 |
|
|
Jul 11 06:15:02 PM PDT 24 |
Jul 11 06:22:32 PM PDT 24 |
5500551600 ps |
| T1103 |
/workspace/coverage/default/10.flash_ctrl_re_evict.4201356761 |
|
|
Jul 11 06:13:54 PM PDT 24 |
Jul 11 06:14:28 PM PDT 24 |
93324800 ps |
| T1104 |
/workspace/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.588747959 |
|
|
Jul 11 06:11:36 PM PDT 24 |
Jul 11 06:12:48 PM PDT 24 |
10038171100 ps |
| T1105 |
/workspace/coverage/default/3.flash_ctrl_hw_rma_reset.1494374952 |
|
|
Jul 11 06:11:58 PM PDT 24 |
Jul 11 06:26:34 PM PDT 24 |
70142190300 ps |
| T1106 |
/workspace/coverage/default/13.flash_ctrl_disable.972229127 |
|
|
Jul 11 06:14:34 PM PDT 24 |
Jul 11 06:14:57 PM PDT 24 |
12695600 ps |
| T1107 |
/workspace/coverage/default/4.flash_ctrl_intr_wr_slow_flash.4091985375 |
|
|
Jul 11 06:12:16 PM PDT 24 |
Jul 11 06:16:02 PM PDT 24 |
92642073000 ps |
| T1108 |
/workspace/coverage/default/78.flash_ctrl_otp_reset.3668505975 |
|
|
Jul 11 06:18:30 PM PDT 24 |
Jul 11 06:20:42 PM PDT 24 |
42506500 ps |
| T1109 |
/workspace/coverage/default/14.flash_ctrl_sec_info_access.2937026289 |
|
|
Jul 11 06:14:51 PM PDT 24 |
Jul 11 06:15:54 PM PDT 24 |
1781936100 ps |
| T1110 |
/workspace/coverage/default/10.flash_ctrl_rw_evict.1873575292 |
|
|
Jul 11 06:13:54 PM PDT 24 |
Jul 11 06:14:26 PM PDT 24 |
51929300 ps |
| T1111 |
/workspace/coverage/default/14.flash_ctrl_hw_rma_reset.1540342786 |
|
|
Jul 11 06:14:45 PM PDT 24 |
Jul 11 06:29:46 PM PDT 24 |
290241285600 ps |
| T1112 |
/workspace/coverage/default/4.flash_ctrl_sw_op.2742985736 |
|
|
Jul 11 06:12:04 PM PDT 24 |
Jul 11 06:12:34 PM PDT 24 |
28597200 ps |
| T1113 |
/workspace/coverage/default/44.flash_ctrl_sec_info_access.2216943463 |
|
|
Jul 11 06:17:53 PM PDT 24 |
Jul 11 06:18:54 PM PDT 24 |
2454631500 ps |
| T1114 |
/workspace/coverage/default/44.flash_ctrl_smoke.3394131717 |
|
|
Jul 11 06:17:50 PM PDT 24 |
Jul 11 06:20:45 PM PDT 24 |
157851700 ps |
| T1115 |
/workspace/coverage/default/28.flash_ctrl_sec_info_access.3672517069 |
|
|
Jul 11 06:16:42 PM PDT 24 |
Jul 11 06:17:47 PM PDT 24 |
526904900 ps |
| T1116 |
/workspace/coverage/default/30.flash_ctrl_otp_reset.3895546593 |
|
|
Jul 11 06:16:52 PM PDT 24 |
Jul 11 06:19:06 PM PDT 24 |
44113300 ps |
| T1117 |
/workspace/coverage/default/29.flash_ctrl_alert_test.4086442276 |
|
|
Jul 11 06:16:51 PM PDT 24 |
Jul 11 06:17:05 PM PDT 24 |
36416600 ps |
| T1118 |
/workspace/coverage/default/3.flash_ctrl_invalid_op.189599636 |
|
|
Jul 11 06:11:56 PM PDT 24 |
Jul 11 06:13:25 PM PDT 24 |
3872916100 ps |
| T1119 |
/workspace/coverage/default/2.flash_ctrl_rw.11306006 |
|
|
Jul 11 06:11:48 PM PDT 24 |
Jul 11 06:20:37 PM PDT 24 |
11852716700 ps |
| T1120 |
/workspace/coverage/default/0.flash_ctrl_intr_rd.1337922578 |
|
|
Jul 11 06:11:34 PM PDT 24 |
Jul 11 06:13:41 PM PDT 24 |
563680400 ps |
| T1121 |
/workspace/coverage/default/14.flash_ctrl_re_evict.2383553114 |
|
|
Jul 11 06:14:49 PM PDT 24 |
Jul 11 06:15:24 PM PDT 24 |
132025600 ps |
| T1122 |
/workspace/coverage/default/0.flash_ctrl_wo.3921052420 |
|
|
Jul 11 06:11:31 PM PDT 24 |
Jul 11 06:14:08 PM PDT 24 |
7768111000 ps |
| T71 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.387112582 |
|
|
Jul 11 06:02:28 PM PDT 24 |
Jul 11 06:03:20 PM PDT 24 |
503773800 ps |
| T258 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.3535320710 |
|
|
Jul 11 06:02:55 PM PDT 24 |
Jul 11 06:03:28 PM PDT 24 |
20547700 ps |
| T259 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.1515288335 |
|
|
Jul 11 06:02:46 PM PDT 24 |
Jul 11 06:03:19 PM PDT 24 |
28404700 ps |
| T260 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.1699082164 |
|
|
Jul 11 06:02:43 PM PDT 24 |
Jul 11 06:03:15 PM PDT 24 |
49069700 ps |
| T72 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.285857390 |
|
|
Jul 11 06:02:26 PM PDT 24 |
Jul 11 06:03:01 PM PDT 24 |
63234800 ps |
| T105 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.328125767 |
|
|
Jul 11 06:02:17 PM PDT 24 |
Jul 11 06:03:44 PM PDT 24 |
17604972300 ps |
| T1123 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2728883326 |
|
|
Jul 11 06:02:12 PM PDT 24 |
Jul 11 06:02:47 PM PDT 24 |
19777100 ps |
| T1124 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2183443801 |
|
|
Jul 11 06:02:26 PM PDT 24 |
Jul 11 06:02:58 PM PDT 24 |
43833400 ps |
| T1125 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.3757294373 |
|
|
Jul 11 06:02:50 PM PDT 24 |
Jul 11 06:03:26 PM PDT 24 |
94471500 ps |
| T1126 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2426127427 |
|
|
Jul 11 06:02:25 PM PDT 24 |
Jul 11 06:02:56 PM PDT 24 |
39593400 ps |
| T106 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.2430739647 |
|
|
Jul 11 06:02:39 PM PDT 24 |
Jul 11 06:03:15 PM PDT 24 |
166012800 ps |
| T1127 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.992576345 |
|
|
Jul 11 06:02:37 PM PDT 24 |
Jul 11 06:03:11 PM PDT 24 |
49353300 ps |
| T110 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.993638578 |
|
|
Jul 11 06:02:18 PM PDT 24 |
Jul 11 06:02:54 PM PDT 24 |
196691300 ps |
| T1128 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.4043480899 |
|
|
Jul 11 06:02:27 PM PDT 24 |
Jul 11 06:03:01 PM PDT 24 |
15214800 ps |
| T73 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.3281772522 |
|
|
Jul 11 06:02:39 PM PDT 24 |
Jul 11 06:03:13 PM PDT 24 |
70943700 ps |
| T325 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.3703147879 |
|
|
Jul 11 06:02:43 PM PDT 24 |
Jul 11 06:03:15 PM PDT 24 |
31543100 ps |
| T1129 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.1539362851 |
|
|
Jul 11 06:02:36 PM PDT 24 |
Jul 11 06:03:10 PM PDT 24 |
44062800 ps |
| T111 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.3778653172 |
|
|
Jul 11 06:02:26 PM PDT 24 |
Jul 11 06:03:01 PM PDT 24 |
63946400 ps |
| T253 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.4164310747 |
|
|
Jul 11 06:02:45 PM PDT 24 |
Jul 11 06:03:18 PM PDT 24 |
31894700 ps |
| T251 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1392652791 |
|
|
Jul 11 06:02:32 PM PDT 24 |
Jul 11 06:03:19 PM PDT 24 |
131905000 ps |
| T254 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3156770338 |
|
|
Jul 11 06:02:12 PM PDT 24 |
Jul 11 06:02:57 PM PDT 24 |
96049700 ps |
| T326 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.94688170 |
|
|
Jul 11 06:02:52 PM PDT 24 |
Jul 11 06:03:25 PM PDT 24 |
15059400 ps |
| T107 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3590491749 |
|
|
Jul 11 06:02:29 PM PDT 24 |
Jul 11 06:18:03 PM PDT 24 |
1743501600 ps |
| T252 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.878945232 |
|
|
Jul 11 06:02:35 PM PDT 24 |
Jul 11 06:03:10 PM PDT 24 |
203743900 ps |
| T327 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1127874155 |
|
|
Jul 11 06:02:48 PM PDT 24 |
Jul 11 06:03:21 PM PDT 24 |
15965100 ps |
| T374 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2869879279 |
|
|
Jul 11 06:02:17 PM PDT 24 |
Jul 11 06:02:53 PM PDT 24 |
99509900 ps |
| T108 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.2071253143 |
|
|
Jul 11 06:02:25 PM PDT 24 |
Jul 11 06:15:11 PM PDT 24 |
1070311800 ps |
| T109 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2864295505 |
|
|
Jul 11 06:02:40 PM PDT 24 |
Jul 11 06:03:18 PM PDT 24 |
183002900 ps |
| T233 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.3885009592 |
|
|
Jul 11 06:02:51 PM PDT 24 |
Jul 11 06:03:30 PM PDT 24 |
200408400 ps |
| T1130 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.1986858281 |
|
|
Jul 11 06:02:51 PM PDT 24 |
Jul 11 06:03:25 PM PDT 24 |
30430400 ps |
| T343 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.3328111617 |
|
|
Jul 11 06:02:18 PM PDT 24 |
Jul 11 06:02:51 PM PDT 24 |
38506900 ps |
| T1131 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.638890513 |
|
|
Jul 11 06:02:39 PM PDT 24 |
Jul 11 06:03:14 PM PDT 24 |
120665700 ps |
| T1132 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.375453391 |
|
|
Jul 11 06:02:27 PM PDT 24 |
Jul 11 06:03:01 PM PDT 24 |
12655400 ps |
| T239 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.2290097510 |
|
|
Jul 11 06:02:38 PM PDT 24 |
Jul 11 06:10:39 PM PDT 24 |
801768000 ps |
| T410 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.720342202 |
|
|
Jul 11 06:02:18 PM PDT 24 |
Jul 11 06:03:30 PM PDT 24 |
2320623900 ps |
| T240 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.133329337 |
|
|
Jul 11 06:02:11 PM PDT 24 |
Jul 11 06:02:43 PM PDT 24 |
58789700 ps |
| T362 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.706045499 |
|
|
Jul 11 06:02:40 PM PDT 24 |
Jul 11 06:03:12 PM PDT 24 |
51259000 ps |
| T234 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.3353128537 |
|
|
Jul 11 06:02:44 PM PDT 24 |
Jul 11 06:03:20 PM PDT 24 |
32632200 ps |
| T1133 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.1927473673 |
|
|
Jul 11 06:02:39 PM PDT 24 |
Jul 11 06:03:14 PM PDT 24 |
25124600 ps |
| T235 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.813767562 |
|
|
Jul 11 06:02:31 PM PDT 24 |
Jul 11 06:03:08 PM PDT 24 |
147177400 ps |
| T411 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.1628736516 |
|
|
Jul 11 06:02:21 PM PDT 24 |
Jul 11 06:03:19 PM PDT 24 |
45992800 ps |
| T1134 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.371034927 |
|
|
Jul 11 06:02:24 PM PDT 24 |
Jul 11 06:03:10 PM PDT 24 |
123752400 ps |
| T1135 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.3211743494 |
|
|
Jul 11 06:02:31 PM PDT 24 |
Jul 11 06:03:04 PM PDT 24 |
14890300 ps |
| T1136 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.741465749 |
|
|
Jul 11 06:02:30 PM PDT 24 |
Jul 11 06:03:03 PM PDT 24 |
10733700 ps |
| T1137 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.3789414853 |
|
|
Jul 11 06:02:16 PM PDT 24 |
Jul 11 06:02:51 PM PDT 24 |
43302700 ps |
| T328 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.3207844213 |
|
|
Jul 11 06:02:55 PM PDT 24 |
Jul 11 06:03:29 PM PDT 24 |
17349800 ps |
| T329 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.450878956 |
|
|
Jul 11 06:02:44 PM PDT 24 |
Jul 11 06:03:17 PM PDT 24 |
49050200 ps |
| T1138 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.4095366416 |
|
|
Jul 11 06:02:41 PM PDT 24 |
Jul 11 06:03:14 PM PDT 24 |
186569300 ps |
| T1139 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.2836716789 |
|
|
Jul 11 06:02:39 PM PDT 24 |
Jul 11 06:03:12 PM PDT 24 |
15467800 ps |
| T330 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.3004220370 |
|
|
Jul 11 06:02:57 PM PDT 24 |
Jul 11 06:03:30 PM PDT 24 |
17343800 ps |
| T1140 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3647305893 |
|
|
Jul 11 06:02:10 PM PDT 24 |
Jul 11 06:02:42 PM PDT 24 |
18321900 ps |
| T1141 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1689194637 |
|
|
Jul 11 06:02:23 PM PDT 24 |
Jul 11 06:02:56 PM PDT 24 |
13694600 ps |
| T1142 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.985380980 |
|
|
Jul 11 06:02:34 PM PDT 24 |
Jul 11 06:03:05 PM PDT 24 |
29049700 ps |
| T290 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.1849569362 |
|
|
Jul 11 06:02:32 PM PDT 24 |
Jul 11 06:03:07 PM PDT 24 |
154215800 ps |
| T1143 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3281727984 |
|
|
Jul 11 06:02:34 PM PDT 24 |
Jul 11 06:03:08 PM PDT 24 |
40653100 ps |
| T236 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.640939075 |
|
|
Jul 11 06:02:27 PM PDT 24 |
Jul 11 06:03:01 PM PDT 24 |
109225600 ps |
| T1144 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.1099600806 |
|
|
Jul 11 06:02:22 PM PDT 24 |
Jul 11 06:02:54 PM PDT 24 |
31547700 ps |
| T1145 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.2674545989 |
|
|
Jul 11 06:02:41 PM PDT 24 |
Jul 11 06:03:13 PM PDT 24 |
18124000 ps |
| T237 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.2191242480 |
|
|
Jul 11 06:02:53 PM PDT 24 |
Jul 11 06:03:29 PM PDT 24 |
109536300 ps |
| T1146 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.1179925771 |
|
|
Jul 11 06:02:35 PM PDT 24 |
Jul 11 06:03:51 PM PDT 24 |
4935590800 ps |
| T412 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3110063936 |
|
|
Jul 11 06:02:34 PM PDT 24 |
Jul 11 06:03:38 PM PDT 24 |
44554900 ps |
| T1147 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.4063555776 |
|
|
Jul 11 06:02:14 PM PDT 24 |
Jul 11 06:02:52 PM PDT 24 |
59223900 ps |
| T238 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.38515556 |
|
|
Jul 11 06:02:48 PM PDT 24 |
Jul 11 06:03:25 PM PDT 24 |
64987600 ps |
| T1148 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.1918620073 |
|
|
Jul 11 06:02:35 PM PDT 24 |
Jul 11 06:03:09 PM PDT 24 |
160887400 ps |
| T1149 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.1042335183 |
|
|
Jul 11 06:02:51 PM PDT 24 |
Jul 11 06:03:25 PM PDT 24 |
20956000 ps |
| T262 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.984441122 |
|
|
Jul 11 06:02:53 PM PDT 24 |
Jul 11 06:03:33 PM PDT 24 |
109265800 ps |
| T256 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.412011537 |
|
|
Jul 11 06:02:24 PM PDT 24 |
Jul 11 06:02:58 PM PDT 24 |
127022700 ps |
| T1150 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.343963437 |
|
|
Jul 11 06:02:24 PM PDT 24 |
Jul 11 06:02:56 PM PDT 24 |
47436400 ps |
| T267 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.1766488503 |
|
|
Jul 11 06:02:39 PM PDT 24 |
Jul 11 06:18:29 PM PDT 24 |
6825948100 ps |
| T291 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1307202628 |
|
|
Jul 11 06:02:31 PM PDT 24 |
Jul 11 06:03:06 PM PDT 24 |
123063000 ps |
| T1151 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.1176585817 |
|
|
Jul 11 06:02:27 PM PDT 24 |
Jul 11 06:03:02 PM PDT 24 |
33100700 ps |
| T1152 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.775529779 |
|
|
Jul 11 06:02:49 PM PDT 24 |
Jul 11 06:03:26 PM PDT 24 |
443274400 ps |
| T257 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.2221967341 |
|
|
Jul 11 06:02:23 PM PDT 24 |
Jul 11 06:03:00 PM PDT 24 |
131595800 ps |
| T269 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3976299678 |
|
|
Jul 11 06:02:39 PM PDT 24 |
Jul 11 06:15:38 PM PDT 24 |
1404219000 ps |
| T1153 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.379135637 |
|
|
Jul 11 06:02:51 PM PDT 24 |
Jul 11 06:03:29 PM PDT 24 |
48435300 ps |
| T1154 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.56286201 |
|
|
Jul 11 06:02:52 PM PDT 24 |
Jul 11 06:03:26 PM PDT 24 |
33254100 ps |
| T364 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.606077688 |
|
|
Jul 11 06:02:30 PM PDT 24 |
Jul 11 06:17:53 PM PDT 24 |
732512200 ps |
| T1155 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.1280993069 |
|
|
Jul 11 06:02:24 PM PDT 24 |
Jul 11 06:02:58 PM PDT 24 |
174116400 ps |
| T1156 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3435902291 |
|
|
Jul 11 06:02:47 PM PDT 24 |
Jul 11 06:03:21 PM PDT 24 |
28525800 ps |
| T1157 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.3166258349 |
|
|
Jul 11 06:02:21 PM PDT 24 |
Jul 11 06:02:54 PM PDT 24 |
14041000 ps |
| T1158 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.1958961977 |
|
|
Jul 11 06:02:23 PM PDT 24 |
Jul 11 06:02:58 PM PDT 24 |
149103600 ps |
| T1159 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.3696466295 |
|
|
Jul 11 06:02:38 PM PDT 24 |
Jul 11 06:03:08 PM PDT 24 |
11575800 ps |
| T372 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.629958303 |
|
|
Jul 11 06:02:31 PM PDT 24 |
Jul 11 06:17:39 PM PDT 24 |
1342338200 ps |
| T1160 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2008140759 |
|
|
Jul 11 06:02:21 PM PDT 24 |
Jul 11 06:03:15 PM PDT 24 |
1299702500 ps |
| T1161 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.3539763869 |
|
|
Jul 11 06:02:42 PM PDT 24 |
Jul 11 06:03:14 PM PDT 24 |
46605400 ps |
| T1162 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.3042346186 |
|
|
Jul 11 06:02:33 PM PDT 24 |
Jul 11 06:03:04 PM PDT 24 |
17339400 ps |
| T292 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.2253103487 |
|
|
Jul 11 06:02:33 PM PDT 24 |
Jul 11 06:03:08 PM PDT 24 |
62933800 ps |
| T1163 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3867942412 |
|
|
Jul 11 06:02:28 PM PDT 24 |
Jul 11 06:03:02 PM PDT 24 |
225701800 ps |
| T1164 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.3251110350 |
|
|
Jul 11 06:02:31 PM PDT 24 |
Jul 11 06:03:55 PM PDT 24 |
1274633900 ps |
| T1165 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.768774150 |
|
|
Jul 11 06:02:30 PM PDT 24 |
Jul 11 06:03:00 PM PDT 24 |
36511300 ps |
| T1166 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.1925936442 |
|
|
Jul 11 06:02:39 PM PDT 24 |
Jul 11 06:03:13 PM PDT 24 |
52154100 ps |
| T1167 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.2567297013 |
|
|
Jul 11 06:02:40 PM PDT 24 |
Jul 11 06:03:15 PM PDT 24 |
20753500 ps |
| T1168 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.1309097856 |
|
|
Jul 11 06:02:40 PM PDT 24 |
Jul 11 06:03:16 PM PDT 24 |
39049400 ps |
| T1169 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.927184202 |
|
|
Jul 11 06:02:30 PM PDT 24 |
Jul 11 06:03:02 PM PDT 24 |
16472100 ps |
| T365 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.886032221 |
|
|
Jul 11 06:02:35 PM PDT 24 |
Jul 11 06:09:18 PM PDT 24 |
211742500 ps |
| T1170 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.1761840895 |
|
|
Jul 11 06:02:52 PM PDT 24 |
Jul 11 06:03:26 PM PDT 24 |
30992100 ps |
| T1171 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.3229503758 |
|
|
Jul 11 06:02:46 PM PDT 24 |
Jul 11 06:03:19 PM PDT 24 |
26519000 ps |
| T293 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.308007604 |
|
|
Jul 11 06:02:17 PM PDT 24 |
Jul 11 06:02:57 PM PDT 24 |
856619100 ps |
| T1172 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.2627592179 |
|
|
Jul 11 06:02:51 PM PDT 24 |
Jul 11 06:03:25 PM PDT 24 |
34568000 ps |
| T1173 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.4247285897 |
|
|
Jul 11 06:02:27 PM PDT 24 |
Jul 11 06:03:01 PM PDT 24 |
24367200 ps |
| T1174 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.3458994985 |
|
|
Jul 11 06:02:31 PM PDT 24 |
Jul 11 06:03:06 PM PDT 24 |
91687200 ps |
| T255 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2883656532 |
|
|
Jul 11 06:02:29 PM PDT 24 |
Jul 11 06:03:03 PM PDT 24 |
34395700 ps |
| T241 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1525195185 |
|
|
Jul 11 06:02:20 PM PDT 24 |
Jul 11 06:02:52 PM PDT 24 |
30344600 ps |
| T242 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.3755668138 |
|
|
Jul 11 06:02:16 PM PDT 24 |
Jul 11 06:02:49 PM PDT 24 |
18297200 ps |
| T1175 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.3505636879 |
|
|
Jul 11 06:02:40 PM PDT 24 |
Jul 11 06:03:15 PM PDT 24 |
35988000 ps |
| T1176 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.2670697538 |
|
|
Jul 11 06:02:30 PM PDT 24 |
Jul 11 06:03:04 PM PDT 24 |
13668500 ps |
| T1177 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.1389325668 |
|
|
Jul 11 06:02:36 PM PDT 24 |
Jul 11 06:03:08 PM PDT 24 |
27398100 ps |
| T1178 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2655571334 |
|
|
Jul 11 06:02:33 PM PDT 24 |
Jul 11 06:03:07 PM PDT 24 |
12472800 ps |
| T1179 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.2912538373 |
|
|
Jul 11 06:02:40 PM PDT 24 |
Jul 11 06:03:32 PM PDT 24 |
64760400 ps |
| T1180 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.4283324916 |
|
|
Jul 11 06:02:42 PM PDT 24 |
Jul 11 06:03:15 PM PDT 24 |
44969400 ps |
| T1181 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2385686070 |
|
|
Jul 11 06:02:17 PM PDT 24 |
Jul 11 06:02:49 PM PDT 24 |
16630000 ps |
| T1182 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3380758834 |
|
|
Jul 11 06:02:45 PM PDT 24 |
Jul 11 06:03:20 PM PDT 24 |
14025800 ps |
| T370 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.3435239806 |
|
|
Jul 11 06:02:38 PM PDT 24 |
Jul 11 06:17:56 PM PDT 24 |
349423000 ps |
| T1183 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1796904653 |
|
|
Jul 11 06:02:49 PM PDT 24 |
Jul 11 06:03:25 PM PDT 24 |
21062800 ps |
| T1184 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.760593481 |
|
|
Jul 11 06:02:26 PM PDT 24 |
Jul 11 06:03:00 PM PDT 24 |
34805500 ps |
| T1185 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.1833293167 |
|
|
Jul 11 06:02:55 PM PDT 24 |
Jul 11 06:03:28 PM PDT 24 |
42345700 ps |
| T1186 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.2143018197 |
|
|
Jul 11 06:02:45 PM PDT 24 |
Jul 11 06:03:18 PM PDT 24 |
49606100 ps |
| T1187 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1441049170 |
|
|
Jul 11 06:02:53 PM PDT 24 |
Jul 11 06:03:29 PM PDT 24 |
34112400 ps |
| T1188 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.1837597672 |
|
|
Jul 11 06:02:59 PM PDT 24 |
Jul 11 06:03:34 PM PDT 24 |
48863800 ps |
| T1189 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.2896047604 |
|
|
Jul 11 06:02:39 PM PDT 24 |
Jul 11 06:03:13 PM PDT 24 |
18342800 ps |
| T1190 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.1389056685 |
|
|
Jul 11 06:02:50 PM PDT 24 |
Jul 11 06:03:28 PM PDT 24 |
71353900 ps |
| T1191 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2129501605 |
|
|
Jul 11 06:02:49 PM PDT 24 |
Jul 11 06:03:25 PM PDT 24 |
82694100 ps |
| T294 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1108754565 |
|
|
Jul 11 06:02:25 PM PDT 24 |
Jul 11 06:03:52 PM PDT 24 |
2980504000 ps |
| T366 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2754435963 |
|
|
Jul 11 06:02:28 PM PDT 24 |
Jul 11 06:10:23 PM PDT 24 |
1680314600 ps |
| T1192 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.2676582924 |
|
|
Jul 11 06:02:40 PM PDT 24 |
Jul 11 06:03:13 PM PDT 24 |
17221700 ps |
| T268 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.3186285445 |
|
|
Jul 11 06:02:31 PM PDT 24 |
Jul 11 06:10:31 PM PDT 24 |
418114300 ps |
| T1193 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.1916325894 |
|
|
Jul 11 06:02:54 PM PDT 24 |
Jul 11 06:03:28 PM PDT 24 |
15439000 ps |
| T295 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.2139706661 |
|
|
Jul 11 06:02:27 PM PDT 24 |
Jul 11 06:03:31 PM PDT 24 |
111279000 ps |
| T1194 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1138995183 |
|
|
Jul 11 06:02:41 PM PDT 24 |
Jul 11 06:03:12 PM PDT 24 |
29878200 ps |
| T363 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.764756208 |
|
|
Jul 11 06:02:38 PM PDT 24 |
Jul 11 06:03:14 PM PDT 24 |
41558500 ps |
| T296 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.3604457824 |
|
|
Jul 11 06:02:22 PM PDT 24 |
Jul 11 06:02:55 PM PDT 24 |
429204900 ps |
| T1195 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.3379725506 |
|
|
Jul 11 06:02:48 PM PDT 24 |
Jul 11 06:03:24 PM PDT 24 |
14334100 ps |
| T1196 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.3387158809 |
|
|
Jul 11 06:02:53 PM PDT 24 |
Jul 11 06:03:26 PM PDT 24 |
62088000 ps |
| T1197 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.221017349 |
|
|
Jul 11 06:02:29 PM PDT 24 |
Jul 11 06:03:04 PM PDT 24 |
251448100 ps |
| T1198 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.1113570866 |
|
|
Jul 11 06:02:29 PM PDT 24 |
Jul 11 06:03:04 PM PDT 24 |
52355800 ps |
| T1199 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.3427806029 |
|
|
Jul 11 06:02:35 PM PDT 24 |
Jul 11 06:03:06 PM PDT 24 |
18565800 ps |
| T1200 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3006765955 |
|
|
Jul 11 06:02:46 PM PDT 24 |
Jul 11 06:03:23 PM PDT 24 |
130601300 ps |
| T1201 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.1423814798 |
|
|
Jul 11 06:02:30 PM PDT 24 |
Jul 11 06:03:06 PM PDT 24 |
416925200 ps |
| T1202 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.1933117701 |
|
|
Jul 11 06:02:14 PM PDT 24 |
Jul 11 06:02:47 PM PDT 24 |
14117000 ps |
| T243 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.3482173234 |
|
|
Jul 11 06:02:10 PM PDT 24 |
Jul 11 06:02:43 PM PDT 24 |
63301700 ps |
| T1203 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.2075425883 |
|
|
Jul 11 06:02:46 PM PDT 24 |
Jul 11 06:03:19 PM PDT 24 |
16369200 ps |
| T1204 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.2248688050 |
|
|
Jul 11 06:02:29 PM PDT 24 |
Jul 11 06:03:03 PM PDT 24 |
36715800 ps |
| T1205 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.1898898697 |
|
|
Jul 11 06:02:36 PM PDT 24 |
Jul 11 06:03:12 PM PDT 24 |
161269000 ps |
| T1206 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3419496265 |
|
|
Jul 11 06:02:36 PM PDT 24 |
Jul 11 06:03:29 PM PDT 24 |
646707300 ps |
| T263 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3840449287 |
|
|
Jul 11 06:03:03 PM PDT 24 |
Jul 11 06:03:38 PM PDT 24 |
35929600 ps |
| T1207 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.2785444525 |
|
|
Jul 11 06:02:29 PM PDT 24 |
Jul 11 06:03:00 PM PDT 24 |
16325100 ps |
| T1208 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.3025986650 |
|
|
Jul 11 06:02:24 PM PDT 24 |
Jul 11 06:02:58 PM PDT 24 |
41767500 ps |
| T1209 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.695532754 |
|
|
Jul 11 06:02:51 PM PDT 24 |
Jul 11 06:09:35 PM PDT 24 |
444100300 ps |
| T1210 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.4173144064 |
|
|
Jul 11 06:02:29 PM PDT 24 |
Jul 11 06:03:01 PM PDT 24 |
27264800 ps |
| T1211 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.3188510146 |
|
|
Jul 11 06:02:40 PM PDT 24 |
Jul 11 06:03:12 PM PDT 24 |
47150800 ps |
| T1212 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1996591267 |
|
|
Jul 11 06:02:25 PM PDT 24 |
Jul 11 06:03:18 PM PDT 24 |
65179300 ps |
| T1213 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.3700287670 |
|
|
Jul 11 06:02:18 PM PDT 24 |
Jul 11 06:02:52 PM PDT 24 |
17762900 ps |
| T297 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.1560289209 |
|
|
Jul 11 06:02:28 PM PDT 24 |
Jul 11 06:03:15 PM PDT 24 |
336557200 ps |
| T1214 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.737529911 |
|
|
Jul 11 06:02:35 PM PDT 24 |
Jul 11 06:03:06 PM PDT 24 |
45143400 ps |
| T1215 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.2735112039 |
|
|
Jul 11 06:02:23 PM PDT 24 |
Jul 11 06:02:59 PM PDT 24 |
29029400 ps |
| T368 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.1446676226 |
|
|
Jul 11 06:02:47 PM PDT 24 |
Jul 11 06:09:33 PM PDT 24 |
350295400 ps |
| T369 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.2583430118 |
|
|
Jul 11 06:02:21 PM PDT 24 |
Jul 11 06:18:03 PM PDT 24 |
6869417500 ps |
| T1216 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.20135237 |
|
|
Jul 11 06:02:39 PM PDT 24 |
Jul 11 06:03:10 PM PDT 24 |
31285600 ps |
| T298 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.3539149066 |
|
|
Jul 11 06:02:36 PM PDT 24 |
Jul 11 06:03:10 PM PDT 24 |
111332000 ps |
| T1217 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.2635361038 |
|
|
Jul 11 06:02:30 PM PDT 24 |
Jul 11 06:03:05 PM PDT 24 |
126507600 ps |
| T1218 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.1275648689 |
|
|
Jul 11 06:02:51 PM PDT 24 |
Jul 11 06:03:26 PM PDT 24 |
26147200 ps |
| T1219 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1091291876 |
|
|
Jul 11 06:02:37 PM PDT 24 |
Jul 11 06:03:08 PM PDT 24 |
16748200 ps |
| T1220 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1127879418 |
|
|
Jul 11 06:02:31 PM PDT 24 |
Jul 11 06:03:05 PM PDT 24 |
35155900 ps |
| T1221 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.4071103468 |
|
|
Jul 11 06:02:23 PM PDT 24 |
Jul 11 06:03:37 PM PDT 24 |
659746500 ps |
| T265 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1603984058 |
|
|
Jul 11 06:02:52 PM PDT 24 |
Jul 11 06:03:28 PM PDT 24 |
55585600 ps |
| T1222 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.503471075 |
|
|
Jul 11 06:02:32 PM PDT 24 |
Jul 11 06:03:07 PM PDT 24 |
33546900 ps |
| T1223 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.3201512866 |
|
|
Jul 11 06:02:56 PM PDT 24 |
Jul 11 06:03:30 PM PDT 24 |
60687300 ps |
| T1224 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.1412938584 |
|
|
Jul 11 06:02:28 PM PDT 24 |
Jul 11 06:02:59 PM PDT 24 |
29694500 ps |
| T1225 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.3094622933 |
|
|
Jul 11 06:02:17 PM PDT 24 |
Jul 11 06:02:53 PM PDT 24 |
419859900 ps |
| T299 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.3931747631 |
|
|
Jul 11 06:02:20 PM PDT 24 |
Jul 11 06:02:56 PM PDT 24 |
100779300 ps |
| T244 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.741482457 |
|
|
Jul 11 06:02:28 PM PDT 24 |
Jul 11 06:02:59 PM PDT 24 |
32438500 ps |
| T1226 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.3248805282 |
|
|
Jul 11 06:02:37 PM PDT 24 |
Jul 11 06:03:12 PM PDT 24 |
221324800 ps |
| T264 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.1278194401 |
|
|
Jul 11 06:02:36 PM PDT 24 |
Jul 11 06:03:10 PM PDT 24 |
39319600 ps |
| T1227 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1613228188 |
|
|
Jul 11 06:02:51 PM PDT 24 |
Jul 11 06:03:29 PM PDT 24 |
110471100 ps |
| T1228 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.1324043655 |
|
|
Jul 11 06:02:26 PM PDT 24 |
Jul 11 06:03:00 PM PDT 24 |
48956600 ps |
| T1229 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.1965263509 |
|
|
Jul 11 06:02:46 PM PDT 24 |
Jul 11 06:03:19 PM PDT 24 |
17311600 ps |
| T1230 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.189603661 |
|
|
Jul 11 06:02:30 PM PDT 24 |
Jul 11 06:03:04 PM PDT 24 |
42024000 ps |
| T367 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1027504451 |
|
|
Jul 11 06:02:21 PM PDT 24 |
Jul 11 06:17:33 PM PDT 24 |
462264400 ps |
| T1231 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.364003981 |
|
|
Jul 11 06:02:37 PM PDT 24 |
Jul 11 06:03:11 PM PDT 24 |
91577700 ps |
| T1232 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.4132185104 |
|
|
Jul 11 06:02:45 PM PDT 24 |
Jul 11 06:03:24 PM PDT 24 |
472412100 ps |
| T1233 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.293974716 |
|
|
Jul 11 06:02:34 PM PDT 24 |
Jul 11 06:03:12 PM PDT 24 |
44377500 ps |
| T1234 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1547755582 |
|
|
Jul 11 06:02:49 PM PDT 24 |
Jul 11 06:03:27 PM PDT 24 |
109447700 ps |
| T1235 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.272648673 |
|
|
Jul 11 06:02:50 PM PDT 24 |
Jul 11 06:03:25 PM PDT 24 |
18644700 ps |
| T1236 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.442813271 |
|
|
Jul 11 06:02:12 PM PDT 24 |
Jul 11 06:02:44 PM PDT 24 |
45405400 ps |
| T1237 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.3345678268 |
|
|
Jul 11 06:02:36 PM PDT 24 |
Jul 11 06:03:07 PM PDT 24 |
40128400 ps |
| T1238 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.441459420 |
|
|
Jul 11 06:02:36 PM PDT 24 |
Jul 11 06:03:07 PM PDT 24 |
24186400 ps |
| T371 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.1875311843 |
|
|
Jul 11 06:02:17 PM PDT 24 |
Jul 11 06:15:06 PM PDT 24 |
1310523800 ps |
| T300 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.3576792787 |
|
|
Jul 11 06:02:48 PM PDT 24 |
Jul 11 06:03:25 PM PDT 24 |
170065100 ps |
| T1239 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.1225346878 |
|
|
Jul 11 06:02:27 PM PDT 24 |
Jul 11 06:02:58 PM PDT 24 |
36951800 ps |
| T1240 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.2061030251 |
|
|
Jul 11 06:02:40 PM PDT 24 |
Jul 11 06:03:40 PM PDT 24 |
337246900 ps |
| T1241 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.1354624539 |
|
|
Jul 11 06:02:37 PM PDT 24 |
Jul 11 06:03:10 PM PDT 24 |
34994100 ps |
| T1242 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.3270680273 |
|
|
Jul 11 06:03:02 PM PDT 24 |
Jul 11 06:03:34 PM PDT 24 |
83044200 ps |
| T301 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.165858830 |
|
|
Jul 11 06:02:24 PM PDT 24 |
Jul 11 06:03:00 PM PDT 24 |
955567500 ps |
| T266 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.928137151 |
|
|
Jul 11 06:02:46 PM PDT 24 |
Jul 11 06:03:21 PM PDT 24 |
65844800 ps |
| T1243 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3305724803 |
|
|
Jul 11 06:02:47 PM PDT 24 |
Jul 11 06:03:25 PM PDT 24 |
124195700 ps |
| T1244 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1929104128 |
|
|
Jul 11 06:02:49 PM PDT 24 |
Jul 11 06:03:22 PM PDT 24 |
128290100 ps |
| T1245 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.787606656 |
|
|
Jul 11 06:02:45 PM PDT 24 |
Jul 11 06:03:18 PM PDT 24 |
47674200 ps |
| T373 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.3898498173 |
|
|
Jul 11 06:02:28 PM PDT 24 |
Jul 11 06:17:44 PM PDT 24 |
2539527600 ps |
| T1246 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.1000361540 |
|
|
Jul 11 06:02:50 PM PDT 24 |
Jul 11 06:03:24 PM PDT 24 |
18627700 ps |
| T1247 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.3654282976 |
|
|
Jul 11 06:02:31 PM PDT 24 |
Jul 11 06:03:07 PM PDT 24 |
169362300 ps |
| T1248 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1475052370 |
|
|
Jul 11 06:02:39 PM PDT 24 |
Jul 11 06:03:14 PM PDT 24 |
19685500 ps |
| T1249 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.1952525228 |
|
|
Jul 11 06:02:31 PM PDT 24 |
Jul 11 06:03:05 PM PDT 24 |
35738300 ps |
| T1250 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.4116441646 |
|
|
Jul 11 06:02:22 PM PDT 24 |
Jul 11 06:10:23 PM PDT 24 |
764800600 ps |
| T1251 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.753290697 |
|
|
Jul 11 06:02:33 PM PDT 24 |
Jul 11 06:03:04 PM PDT 24 |
50600500 ps |