Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	341460	1		T1	2		T2	155		T3	1
all_values[1]	341460	1		T1	2		T2	155		T3	1
all_values[2]	341460	1		T1	2		T2	155		T3	1
all_values[3]	341460	1		T1	2		T2	155		T3	1
all_values[4]	341460	1		T1	2		T2	155		T3	1
all_values[5]	341460	1		T1	2		T2	155		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	689019	1		T1	12		T2	314		T3	6
auto[1]	1359741	1		T2	616		T6	12832		T26	6148

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1009364	1		T1	7		T2	466		T3	4
auto[1]	1039396	1		T1	5		T2	464		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	341299	1		T1	2		T2	155		T3	1
all_values[0]	auto[1]	auto[1]	161	1		T245	2		T247	2		T305	7
all_values[1]	auto[0]	auto[1]	341309	1		T1	2		T2	155		T3	1
all_values[1]	auto[1]	auto[1]	151	1		T245	4		T246	1		T247	7
all_values[2]	auto[0]	auto[0]	1559	1		T1	2		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	65	1		T245	1		T246	1		T247	2
all_values[2]	auto[1]	auto[0]	339774	1		T2	154		T6	3208		T26	1537
all_values[2]	auto[1]	auto[1]	62	1		T245	1		T246	1		T247	3
all_values[3]	auto[0]	auto[0]	1527	1		T1	2		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	54	1		T245	2		T246	3		T247	3
all_values[3]	auto[1]	auto[0]	84242	1		T2	77		T6	1604		T26	1537
all_values[3]	auto[1]	auto[1]	255637	1		T2	77		T6	1604		T34	1535
all_values[4]	auto[0]	auto[0]	1100	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	496	1		T1	1		T17	1		T53	1
all_values[4]	auto[1]	auto[0]	239875	1		T2	77		T6	1604		T26	1
all_values[4]	auto[1]	auto[1]	99989	1		T2	77		T6	1604		T26	1536
all_values[5]	auto[0]	auto[0]	1500	1		T1	2		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	110	1		T5	1		T35	1		T36	1
all_values[5]	auto[1]	auto[0]	339787	1		T2	154		T6	3208		T26	1537
all_values[5]	auto[1]	auto[1]	63	1		T245	1		T246	2		T305	1