Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	246854	1		T1	100		T2	48		T4	707
auto[FlashEraseBank]	271728	1		T1	1290		T2	29		T17	1

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	255392	1		T1	451		T2	77		T4	361
auto[FlashOpProgram]	243383	1		T1	890		T4	173		T17	1
auto[FlashOpErase]	15807	1		T1	49		T4	173		T53	1
auto[FlashOpInvalid]	4000	1		T137	200		T208	200		T228	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	255392	1		T1	451		T2	77		T4	361
op[FlashOpProgram]	243383	1		T1	890		T4	173		T17	1
op[FlashOpErase]	15807	1		T1	49		T4	173		T53	1
read_erase_read	561	1		T1	7		T25	14		T38	1
read_prog_read	861	1		T1	3		T20	1		T5	3

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	374927	1		T1	90		T17	3		T20	1
auto[FlashPartInfo]	139717	1		T1	1300		T4	707		T20	10
auto[FlashPartInfo1]	985	1		T2	33		T33	64		T38	4
auto[FlashPartInfo2]	2953	1		T2	44		T20	1		T23	2

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	182010	1		T1	30		T17	2		T20	1
auto[FlashPartData]	auto[FlashOpProgram]	185373	1		T1	24		T17	1		T5	374
auto[FlashPartData]	auto[FlashOpErase]	3626	1		T1	36		T53	1		T15	1
auto[FlashPartData]	auto[FlashOpInvalid]	3918	1		T137	196		T208	198		T228	198
auto[FlashPartInfo]	auto[FlashOpRead]	70519	1		T1	421		T4	361		T20	9
auto[FlashPartInfo]	auto[FlashOpProgram]	56965	1		T1	866		T4	173		T20	1
auto[FlashPartInfo]	auto[FlashOpErase]	12163	1		T1	13		T4	173		T45	388
auto[FlashPartInfo]	auto[FlashOpInvalid]	70	1		T137	4		T208	2		T228	2
auto[FlashPartInfo1]	auto[FlashOpRead]	807	1		T2	33		T33	32		T38	4
auto[FlashPartInfo1]	auto[FlashOpProgram]	168	1		T33	32		T140	32		T142	2
auto[FlashPartInfo1]	auto[FlashOpErase]	4	1		T141	1		T143	1		T376	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	6	1		T143	2		T376	2		T126	2
auto[FlashPartInfo2]	auto[FlashOpRead]	2056	1		T2	44		T20	1		T23	2
auto[FlashPartInfo2]	auto[FlashOpProgram]	877	1		T33	64		T38	5		T26	5
auto[FlashPartInfo2]	auto[FlashOpErase]	14	1		T200	1		T131	1		T377	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	6	1		T377	2		T378	2		T379	2