Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31455	1		T1	12		T4	352		T45	804
auto[1]	31	1		T266	10		T380	1		T381	1
auto[2]	74	1		T23	1		T200	3		T136	12
auto[3]	292	1		T23	1		T25	17		T24	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7970	1		T1	3		T4	88		T23	1
evic_idx[1]	7970	1		T1	3		T4	88		T45	201
evic_idx[2]	7950	1		T1	3		T4	88		T45	201
evic_idx[3]	7962	1		T1	3		T4	88		T23	1

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	30954	1		T4	352		T45	804		T25	17
evic_op[2]	324	1		T23	2		T24	1		T37	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7668	1		T4	88		T45	201		T382	1
evic_idx[0]	evic_op[1]	auto[1]	6	1		T266	3		T383	2		T384	1
evic_idx[0]	evic_op[1]	auto[2]	5	1		T266	3		T385	2		-	-
evic_idx[0]	evic_op[1]	auto[3]	67	1		T25	5		T266	1		T260	2
evic_idx[0]	evic_op[2]	auto[0]	64	1		T367	1		T386	4		T387	1
evic_idx[0]	evic_op[2]	auto[1]	3	1		T72	1		T388	1		T389	1
evic_idx[0]	evic_op[2]	auto[2]	5	1		T23	1		T390	2		T391	1
evic_idx[0]	evic_op[2]	auto[3]	8	1		T392	1		T393	1		T394	1
evic_idx[1]	evic_op[1]	auto[0]	7666	1		T4	88		T45	201		T382	1
evic_idx[1]	evic_op[1]	auto[1]	6	1		T266	3		T395	1		T383	1
evic_idx[1]	evic_op[1]	auto[2]	6	1		T200	2		T266	2		T395	1
evic_idx[1]	evic_op[1]	auto[3]	64	1		T25	4		T266	1		T260	4
evic_idx[1]	evic_op[2]	auto[0]	68	1		T192	1		T212	1		T367	1
evic_idx[1]	evic_op[2]	auto[1]	4	1		T380	1		T72	1		T396	1
evic_idx[1]	evic_op[2]	auto[2]	1	1		T397	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[3]	11	1		T37	1		T398	1		T297	1
evic_idx[2]	evic_op[1]	auto[0]	7665	1		T4	88		T45	201		T382	1
evic_idx[2]	evic_op[1]	auto[1]	4	1		T266	2		T383	1		T384	1
evic_idx[2]	evic_op[1]	auto[2]	5	1		T266	2		T399	1		T395	1
evic_idx[2]	evic_op[1]	auto[3]	57	1		T25	4		T200	1		T266	1
evic_idx[2]	evic_op[2]	auto[0]	61	1		T367	1		T386	4		T387	1
evic_idx[2]	evic_op[2]	auto[1]	2	1		T381	1		T400	1		-	-
evic_idx[2]	evic_op[2]	auto[2]	1	1		T396	1		-	-		-	-
evic_idx[2]	evic_op[2]	auto[3]	12	1		T24	1		T401	1		T402	1
evic_idx[3]	evic_op[1]	auto[0]	7664	1		T4	88		T45	201		T382	1
evic_idx[3]	evic_op[1]	auto[1]	3	1		T266	2		T383	1		-	-
evic_idx[3]	evic_op[1]	auto[2]	10	1		T200	1		T266	3		T399	2
evic_idx[3]	evic_op[1]	auto[3]	58	1		T25	4		T200	1		T260	2
evic_idx[3]	evic_op[2]	auto[0]	61	1		T367	1		T386	4		T387	1
evic_idx[3]	evic_op[2]	auto[1]	3	1		T261	1		T403	1		T389	1
evic_idx[3]	evic_op[2]	auto[2]	5	1		T398	1		T390	2		T396	1
evic_idx[3]	evic_op[2]	auto[3]	15	1		T23	1		T255	1		T265	1