Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

---

Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	47348	1		T175	16061		T310	14703		T311	8235
rd_lvl[2]	34924	1		T175	12099		T207	540		T312	891
rd_lvl[3]	13662	1		T207	42		T211	795		T312	1941
rd_lvl[4]	22111	1		T211	1074		T313	1155		T314	5154
rd_lvl[5]	15879	1		T77	2269		T211	95		T313	445
rd_lvl[6]	20626	1		T77	2623		T211	227		T315	29
rd_lvl[7]	8744	1		T211	112		T313	131		T315	207
rd_lvl[8]	10365	1		T77	1		T316	2917		T211	18
rd_lvl[9]	3465	1		T316	391		T313	1		T315	1
rd_lvl[10]	4524	1		T60	1351		T313	1		T315	2
rd_lvl[11]	2856	1		T34	493		T60	481		T31	212
rd_lvl[12]	8814	1		T34	1042		T31	66		T317	66
rd_lvl[13]	2760	1		T6	580		T317	10		T318	179
rd_lvl[14]	6724	1		T6	1024		T31	2		T78	1
rd_lvl[15]	2687	1		T2	59		T32	610		T317	2