Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	341460	1		T1	2		T2	155		T3	1
all_pins[1]	341460	1		T1	2		T2	155		T3	1
all_pins[2]	341460	1		T1	2		T2	155		T3	1
all_pins[3]	341460	1		T1	2		T2	155		T3	1
all_pins[4]	341460	1		T1	2		T2	155		T3	1
all_pins[5]	341460	1		T1	2		T2	155		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1729959	1		T1	12		T2	740		T3	6
values[0x1]	318801	1		T2	190		T6	3208		T26	1536
transitions[0x0=>0x1]	291942	1		T2	154		T6	3208		T26	1536
transitions[0x1=>0x0]	291930	1		T2	154		T6	3208		T26	1536

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	341299	1		T1	2		T2	155		T3	1
all_pins[0]	values[0x1]	161	1		T245	2		T247	2		T305	7
all_pins[0]	transitions[0x0=>0x1]	89	1		T247	1		T305	2		T306	1
all_pins[0]	transitions[0x1=>0x0]	79	1		T245	2		T246	1		T247	6
all_pins[1]	values[0x0]	341309	1		T1	2		T2	155		T3	1
all_pins[1]	values[0x1]	151	1		T245	4		T246	1		T247	7
all_pins[1]	transitions[0x0=>0x1]	119	1		T245	3		T247	5		T305	5
all_pins[1]	transitions[0x1=>0x0]	1788	1		T2	18		T32	1084		T321	266
all_pins[2]	values[0x0]	339640	1		T1	2		T2	137		T3	1
all_pins[2]	values[0x1]	1820	1		T2	18		T32	1084		T321	266
all_pins[2]	transitions[0x0=>0x1]	46	1		T245	1		T246	1		T247	3
all_pins[2]	transitions[0x1=>0x0]	205548	1		T2	59		T6	1604		T34	1535
all_pins[3]	values[0x0]	134138	1		T1	2		T2	78		T3	1
all_pins[3]	values[0x1]	207322	1		T2	77		T6	1604		T34	1535
all_pins[3]	transitions[0x0=>0x1]	182401	1		T2	59		T6	1604		T34	1535
all_pins[3]	transitions[0x1=>0x0]	84363	1		T2	77		T6	1604		T26	1536
all_pins[4]	values[0x0]	232176	1		T1	2		T2	60		T3	1
all_pins[4]	values[0x1]	109284	1		T2	95		T6	1604		T26	1536
all_pins[4]	transitions[0x0=>0x1]	109266	1		T2	95		T6	1604		T26	1536
all_pins[4]	transitions[0x1=>0x0]	45	1		T245	1		T246	2		T305	1
all_pins[5]	values[0x0]	341397	1		T1	2		T2	155		T3	1
all_pins[5]	values[0x1]	63	1		T245	1		T246	2		T305	1
all_pins[5]	transitions[0x0=>0x1]	21	1		T245	1		T246	2		T308	1
all_pins[5]	transitions[0x1=>0x0]	107	1		T245	2		T247	2		T305	5