Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	275	1		T245	7		T246	4		T247	7
all_values[1]	275	1		T245	7		T246	4		T247	7
all_values[2]	275	1		T245	7		T246	4		T247	7
all_values[3]	275	1		T245	7		T246	4		T247	7
all_values[4]	275	1		T245	7		T246	4		T247	7
all_values[5]	275	1		T245	7		T246	4		T247	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	903	1		T245	24		T246	20		T247	21
auto[1]	747	1		T245	18		T246	4		T247	21

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	517	1		T245	18		T246	7		T247	14
auto[1]	1133	1		T245	24		T246	17		T247	28

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	970	1		T245	26		T246	14		T247	24
auto[1]	680	1		T245	16		T246	10		T247	18

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	79	1		T245	4		T246	3		T247	3
all_values[0]	auto[0]	auto[1]	auto[1]	83	1		T245	1		T305	3		T306	3
all_values[0]	auto[1]	auto[0]	auto[1]	66	1		T245	1		T246	1		T247	2
all_values[0]	auto[1]	auto[1]	auto[1]	47	1		T245	1		T247	2		T305	3
all_values[1]	auto[0]	auto[0]	auto[1]	96	1		T245	2		T246	2		T247	1
all_values[1]	auto[0]	auto[1]	auto[1]	73	1		T247	4		T305	1		T306	1
all_values[1]	auto[1]	auto[0]	auto[1]	57	1		T245	1		T246	2		T305	2
all_values[1]	auto[1]	auto[1]	auto[1]	49	1		T245	4		T247	2		T305	1
all_values[2]	auto[0]	auto[0]	auto[0]	90	1		T245	4		T246	2		T247	2
all_values[2]	auto[0]	auto[1]	auto[0]	58	1		T245	1		T305	3		T307	2
all_values[2]	auto[1]	auto[0]	auto[1]	74	1		T245	2		T246	2		T247	2
all_values[2]	auto[1]	auto[1]	auto[1]	53	1		T247	3		T305	2		T307	1
all_values[3]	auto[0]	auto[0]	auto[0]	76	1		T245	5		T246	1		T247	2
all_values[3]	auto[0]	auto[1]	auto[0]	91	1		T247	2		T305	3		T306	2
all_values[3]	auto[1]	auto[0]	auto[1]	58	1		T245	2		T246	3		T247	2
all_values[3]	auto[1]	auto[1]	auto[1]	50	1		T247	1		T308	1		T309	1
all_values[4]	auto[0]	auto[0]	auto[0]	62	1		T245	1		T247	3		T307	1
all_values[4]	auto[0]	auto[0]	auto[1]	30	1		T246	1		T305	3		T306	1
all_values[4]	auto[0]	auto[1]	auto[0]	42	1		T245	4		T246	2		T247	1
all_values[4]	auto[0]	auto[1]	auto[1]	25	1		T306	1		T307	1		T308	1
all_values[4]	auto[1]	auto[0]	auto[1]	60	1		T246	1		T305	2		T306	1
all_values[4]	auto[1]	auto[1]	auto[1]	56	1		T245	2		T247	3		T305	2
all_values[5]	auto[0]	auto[0]	auto[0]	55	1		T246	2		T247	1		T306	2
all_values[5]	auto[0]	auto[0]	auto[1]	38	1		T247	2		T305	2		T307	1
all_values[5]	auto[0]	auto[1]	auto[0]	43	1		T245	3		T247	3		T305	1
all_values[5]	auto[0]	auto[1]	auto[1]	29	1		T245	1		T246	1		T305	1
all_values[5]	auto[1]	auto[0]	auto[1]	62	1		T245	2		T247	1		T305	3
all_values[5]	auto[1]	auto[1]	auto[1]	48	1		T245	1		T246	1		T306	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal