Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	276316	1		T2	2		T3	1		T5	2
all_values[1]	276316	1		T2	2		T3	1		T5	2
all_values[2]	276316	1		T2	2		T3	1		T5	2
all_values[3]	276316	1		T2	2		T3	1		T5	2
all_values[4]	276316	1		T2	2		T3	1		T5	2
all_values[5]	276316	1		T2	2		T3	1		T5	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	558825	1		T2	12		T3	6		T5	12
auto[1]	1099071	1		T4	6848		T21	4096		T24	936

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	809519	1		T2	7		T3	4		T5	7
auto[1]	848377	1		T2	5		T3	2		T5	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	276176	1		T2	2		T3	1		T5	2
all_values[0]	auto[1]	auto[1]	140	1		T269	5		T270	1		T329	5
all_values[1]	auto[0]	auto[1]	276173	1		T2	2		T3	1		T5	2
all_values[1]	auto[1]	auto[1]	143	1		T269	7		T270	1		T331	4
all_values[2]	auto[0]	auto[0]	1564	1		T2	2		T3	1		T5	2
all_values[2]	auto[0]	auto[1]	49	1		T269	3		T270	2		T329	1
all_values[2]	auto[1]	auto[0]	274640	1		T4	1712		T21	1024		T24	234
all_values[2]	auto[1]	auto[1]	63	1		T270	1		T331	1		T330	1
all_values[3]	auto[0]	auto[0]	1569	1		T2	2		T3	1		T5	2
all_values[3]	auto[0]	auto[1]	57	1		T269	2		T270	1		T329	1
all_values[3]	auto[1]	auto[0]	77105	1		T4	856		T21	512		T24	78
all_values[3]	auto[1]	auto[1]	197585	1		T4	856		T21	512		T24	156
all_values[4]	auto[0]	auto[0]	1120	1		T2	1		T3	1		T5	1
all_values[4]	auto[0]	auto[1]	505	1		T2	1		T5	1		T16	1
all_values[4]	auto[1]	auto[0]	177370	1		T4	856		T21	512		T24	156
all_values[4]	auto[1]	auto[1]	97321	1		T4	856		T21	512		T24	78
all_values[5]	auto[0]	auto[0]	1517	1		T2	2		T3	1		T5	2
all_values[5]	auto[0]	auto[1]	95	1		T16	1		T18	1		T33	1
all_values[5]	auto[1]	auto[0]	274634	1		T4	1712		T21	1024		T24	234
all_values[5]	auto[1]	auto[1]	70	1		T269	2		T331	2		T332	3