Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	1	15	93.75

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	1	15	93.75	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	242340	1		T1	1		T2	991		T3	1492
auto[FlashEraseBank]	270633	1		T2	909		T5	565		T4	378

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	256747	1		T3	746		T5	1015		T4	856
auto[FlashOpProgram]	236380	1		T1	1		T2	1900		T3	373
auto[FlashOpErase]	15846	1		T3	373		T29	10		T30	8
auto[FlashOpInvalid]	4000	1		T78	200		T150	200		T145	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	256747	1		T3	746		T5	1015		T4	856
op[FlashOpProgram]	236380	1		T1	1		T2	1900		T3	373
op[FlashOpErase]	15846	1		T3	373		T29	10		T30	8
read_erase_read	558	1		T29	3		T30	2		T54	3
read_prog_read	919	1		T52	7		T54	4		T22	2

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	369957	1		T1	1		T2	1679		T5	777
auto[FlashPartInfo]	139050	1		T2	217		T3	1492		T5	229
auto[FlashPartInfo1]	857	1		T5	1		T4	18		T16	3
auto[FlashPartInfo2]	3109	1		T2	4		T5	8		T4	12

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for op_part_cross

Uncovered bins

part_cp	op_cp	COUNT	AT LEAST	NUMBER
[auto[FlashPartInfo1]]	[auto[FlashOpInvalid]]	0	1	1

Covered bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	183467	1		T5	777		T4	826		T16	927
auto[FlashPartData]	auto[FlashOpProgram]	178994	1		T1	1		T2	1679		T18	92
auto[FlashPartData]	auto[FlashOpErase]	3588	1		T36	5		T52	9		T53	26
auto[FlashPartData]	auto[FlashOpInvalid]	3908	1		T78	198		T150	196		T145	192
auto[FlashPartInfo]	auto[FlashOpRead]	70421	1		T3	746		T5	229		T16	233
auto[FlashPartInfo]	auto[FlashOpProgram]	56317	1		T2	217		T3	373		T18	55
auto[FlashPartInfo]	auto[FlashOpErase]	12236	1		T3	373		T29	10		T30	8
auto[FlashPartInfo]	auto[FlashOpInvalid]	76	1		T78	2		T150	4		T145	6
auto[FlashPartInfo1]	auto[FlashOpRead]	694	1		T5	1		T4	18		T16	3
auto[FlashPartInfo1]	auto[FlashOpProgram]	162	1		T158	32		T132	32		T134	32
auto[FlashPartInfo1]	auto[FlashOpErase]	1	1		T345	1		-	-		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	2165	1		T5	8		T4	12		T16	9
auto[FlashPartInfo2]	auto[FlashOpProgram]	907	1		T2	4		T18	4		T50	4
auto[FlashPartInfo2]	auto[FlashOpErase]	21	1		T145	1		T141	1		T127	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	16	1		T145	2		T141	2		T346	2