Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31227	1		T3	760		T36	2		T52	4
auto[1]	23	1		T22	1		T34	1		T209	1
auto[2]	46	1		T209	1		T169	8		T129	4
auto[3]	254	1		T35	1		T223	1		T152	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7896	1		T3	190		T36	1		T52	1
evic_idx[1]	7892	1		T3	190		T52	1		T53	1
evic_idx[2]	7883	1		T3	190		T52	1		T53	1
evic_idx[3]	7879	1		T3	190		T36	1		T52	1

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	30713	1		T3	760		T36	1		T96	688
evic_op[2]	289	1		T36	1		T22	1		T64	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7614	1		T3	190		T96	172		T97	184
evic_idx[0]	evic_op[1]	auto[1]	6	1		T403	6		-	-		-	-
evic_idx[0]	evic_op[1]	auto[2]	8	1		T404	2		T405	1		T406	5
evic_idx[0]	evic_op[1]	auto[3]	60	1		T219	3		T289	2		T407	2
evic_idx[0]	evic_op[2]	auto[0]	60	1		T36	1		T57	4		T392	1
evic_idx[0]	evic_op[2]	auto[1]	2	1		T408	1		T409	1		-	-
evic_idx[0]	evic_op[2]	auto[2]	3	1		T410	1		T411	2		-	-
evic_idx[0]	evic_op[2]	auto[3]	5	1		T220	1		T412	1		T413	1
evic_idx[1]	evic_op[1]	auto[0]	7611	1		T3	190		T96	172		T97	184
evic_idx[1]	evic_op[1]	auto[1]	4	1		T403	4		-	-		-	-
evic_idx[1]	evic_op[1]	auto[2]	7	1		T414	2		T404	2		T406	3
evic_idx[1]	evic_op[1]	auto[3]	58	1		T219	3		T289	5		T415	2
evic_idx[1]	evic_op[2]	auto[0]	64	1		T64	1		T57	4		T227	1
evic_idx[1]	evic_op[2]	auto[1]	1	1		T22	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[2]	2	1		T209	1		T416	1		-	-
evic_idx[1]	evic_op[2]	auto[3]	8	1		T223	1		T152	1		T417	1
evic_idx[2]	evic_op[1]	auto[0]	7612	1		T3	190		T96	172		T97	184
evic_idx[2]	evic_op[1]	auto[1]	4	1		T403	4		-	-		-	-
evic_idx[2]	evic_op[1]	auto[2]	5	1		T404	2		T406	3		-	-
evic_idx[2]	evic_op[1]	auto[3]	58	1		T219	3		T289	6		T415	1
evic_idx[2]	evic_op[2]	auto[0]	57	1		T231	1		T57	4		T392	1
evic_idx[2]	evic_op[2]	auto[1]	1	1		T209	1		-	-		-	-
evic_idx[2]	evic_op[2]	auto[2]	1	1		T411	1		-	-		-	-
evic_idx[2]	evic_op[2]	auto[3]	8	1		T35	1		T418	1		T419	1
evic_idx[3]	evic_op[1]	auto[0]	7613	1		T3	190		T36	1		T96	172
evic_idx[3]	evic_op[1]	auto[1]	3	1		T403	3		-	-		-	-
evic_idx[3]	evic_op[1]	auto[2]	4	1		T404	2		T406	2		-	-
evic_idx[3]	evic_op[1]	auto[3]	46	1		T219	3		T289	1		T415	1
evic_idx[3]	evic_op[2]	auto[0]	60	1		T152	1		T57	4		T392	1
evic_idx[3]	evic_op[2]	auto[1]	2	1		T34	1		T420	1		-	-
evic_idx[3]	evic_op[2]	auto[2]	4	1		T410	1		T411	2		T421	1
evic_idx[3]	evic_op[2]	auto[3]	11	1		T372	1		T139	1		T422	1