Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	17961	1		T123	2258		T336	15703		-	-
rd_lvl[2]	28013	1		T123	867		T336	11801		T337	1329
rd_lvl[3]	10840	1		T123	357		T338	330		T294	1234
rd_lvl[4]	33213	1		T123	210		T339	5496		T338	96
rd_lvl[5]	17674	1		T140	181		T295	717		T123	76
rd_lvl[6]	17813	1		T340	1323		T140	58		T295	2541
rd_lvl[7]	6554	1		T24	118		T340	480		T295	1105
rd_lvl[8]	12145	1		T24	38		T340	43		T140	2
rd_lvl[9]	4726	1		T291	463		T341	589		T222	242
rd_lvl[10]	5911	1		T291	1205		T341	1063		T222	1325
rd_lvl[11]	3288	1		T21	268		T140	1		T123	44
rd_lvl[12]	3431	1		T21	180		T32	288		T342	1219
rd_lvl[13]	1437	1		T32	249		T342	404		T338	2
rd_lvl[14]	6566	1		T21	64		T343	52		T123	44
rd_lvl[15]	5541	1		T4	355		T32	1		T290	274