Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	276316	1		T2	2		T3	1		T5	2
all_pins[1]	276316	1		T2	2		T3	1		T5	2
all_pins[2]	276316	1		T2	2		T3	1		T5	2
all_pins[3]	276316	1		T2	2		T3	1		T5	2
all_pins[4]	276316	1		T2	2		T3	1		T5	2
all_pins[5]	276316	1		T2	2		T3	1		T5	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1366710	1		T2	12		T3	6		T5	12
values[0x1]	291186	1		T4	2714		T21	1024		T24	234
transitions[0x0=>0x1]	257010	1		T4	1712		T21	1024		T24	234
transitions[0x1=>0x0]	257001	1		T4	1712		T21	1024		T24	234

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	276176	1		T2	2		T3	1		T5	2
all_pins[0]	values[0x1]	140	1		T269	5		T270	1		T329	5
all_pins[0]	transitions[0x0=>0x1]	81	1		T269	1		T270	1		T329	5
all_pins[0]	transitions[0x1=>0x0]	84	1		T269	3		T270	1		T330	4
all_pins[1]	values[0x0]	276173	1		T2	2		T3	1		T5	2
all_pins[1]	values[0x1]	143	1		T269	7		T270	1		T331	4
all_pins[1]	transitions[0x0=>0x1]	108	1		T269	7		T270	1		T331	3
all_pins[1]	transitions[0x1=>0x0]	4274	1		T4	501		T290	220		T343	2
all_pins[2]	values[0x0]	272007	1		T2	2		T3	1		T5	2
all_pins[2]	values[0x1]	4309	1		T4	501		T290	220		T343	2
all_pins[2]	transitions[0x0=>0x1]	48	1		T270	1		T331	1		T335	1
all_pins[2]	transitions[0x1=>0x0]	175295	1		T4	355		T21	512		T24	156
all_pins[3]	values[0x0]	96760	1		T2	2		T3	1		T5	2
all_pins[3]	values[0x1]	179556	1		T4	856		T21	512		T24	156
all_pins[3]	transitions[0x0=>0x1]	149786	1		T4	355		T21	512		T24	156
all_pins[3]	transitions[0x1=>0x0]	77198	1		T4	856		T21	512		T24	78
all_pins[4]	values[0x0]	169348	1		T2	2		T3	1		T5	2
all_pins[4]	values[0x1]	106968	1		T4	1357		T21	512		T24	78
all_pins[4]	transitions[0x0=>0x1]	106955	1		T4	1357		T21	512		T24	78
all_pins[4]	transitions[0x1=>0x0]	57	1		T269	2		T331	2		T332	2
all_pins[5]	values[0x0]	276246	1		T2	2		T3	1		T5	2
all_pins[5]	values[0x1]	70	1		T269	2		T331	2		T332	3
all_pins[5]	transitions[0x0=>0x1]	32	1		T269	1		T331	1		T335	1
all_pins[5]	transitions[0x1=>0x0]	93	1		T269	3		T270	1		T329	4