| T1080 |
/workspace/coverage/default/4.flash_ctrl_sec_info_access.4108373832 |
|
|
Jul 13 07:19:38 PM PDT 24 |
Jul 13 07:20:42 PM PDT 24 |
419718500 ps |
| T1081 |
/workspace/coverage/default/19.flash_ctrl_lcmgr_intg.2095979000 |
|
|
Jul 13 07:21:49 PM PDT 24 |
Jul 13 07:22:04 PM PDT 24 |
212969900 ps |
| T1082 |
/workspace/coverage/default/15.flash_ctrl_sec_info_access.43604530 |
|
|
Jul 13 07:21:13 PM PDT 24 |
Jul 13 07:22:23 PM PDT 24 |
1195454600 ps |
| T1083 |
/workspace/coverage/default/4.flash_ctrl_host_dir_rd.2100539338 |
|
|
Jul 13 07:19:47 PM PDT 24 |
Jul 13 07:21:08 PM PDT 24 |
162907400 ps |
| T1084 |
/workspace/coverage/default/28.flash_ctrl_disable.1454460059 |
|
|
Jul 13 07:22:36 PM PDT 24 |
Jul 13 07:23:00 PM PDT 24 |
16096900 ps |
| T1085 |
/workspace/coverage/default/17.flash_ctrl_invalid_op.3651024295 |
|
|
Jul 13 07:21:26 PM PDT 24 |
Jul 13 07:22:58 PM PDT 24 |
3865225900 ps |
| T1086 |
/workspace/coverage/default/61.flash_ctrl_otp_reset.1666616011 |
|
|
Jul 13 07:23:56 PM PDT 24 |
Jul 13 07:25:48 PM PDT 24 |
78778900 ps |
| T1087 |
/workspace/coverage/default/1.flash_ctrl_sw_op.2083610398 |
|
|
Jul 13 07:18:47 PM PDT 24 |
Jul 13 07:19:36 PM PDT 24 |
45647200 ps |
| T1088 |
/workspace/coverage/default/3.flash_ctrl_rw_serr.3499637460 |
|
|
Jul 13 07:19:25 PM PDT 24 |
Jul 13 07:28:21 PM PDT 24 |
3362268200 ps |
| T1089 |
/workspace/coverage/default/8.flash_ctrl_sec_info_access.604577296 |
|
|
Jul 13 07:20:05 PM PDT 24 |
Jul 13 07:21:03 PM PDT 24 |
3453703000 ps |
| T1090 |
/workspace/coverage/default/4.flash_ctrl_sw_op.2055576615 |
|
|
Jul 13 07:19:33 PM PDT 24 |
Jul 13 07:20:03 PM PDT 24 |
22231600 ps |
| T1091 |
/workspace/coverage/default/0.flash_ctrl_ro.704295243 |
|
|
Jul 13 07:18:41 PM PDT 24 |
Jul 13 07:21:02 PM PDT 24 |
2433054700 ps |
| T1092 |
/workspace/coverage/default/13.flash_ctrl_lcmgr_intg.2308494977 |
|
|
Jul 13 07:20:53 PM PDT 24 |
Jul 13 07:21:11 PM PDT 24 |
15358900 ps |
| T1093 |
/workspace/coverage/default/1.flash_ctrl_serr_counter.299067996 |
|
|
Jul 13 07:18:49 PM PDT 24 |
Jul 13 07:20:36 PM PDT 24 |
3692551200 ps |
| T1094 |
/workspace/coverage/default/13.flash_ctrl_wo.1326626011 |
|
|
Jul 13 07:20:46 PM PDT 24 |
Jul 13 07:23:49 PM PDT 24 |
9009969700 ps |
| T1095 |
/workspace/coverage/default/20.flash_ctrl_rw_evict.3670748704 |
|
|
Jul 13 07:22:02 PM PDT 24 |
Jul 13 07:22:36 PM PDT 24 |
72730300 ps |
| T1096 |
/workspace/coverage/default/12.flash_ctrl_rw.3638646086 |
|
|
Jul 13 07:20:40 PM PDT 24 |
Jul 13 07:29:19 PM PDT 24 |
3820573300 ps |
| T409 |
/workspace/coverage/default/14.flash_ctrl_rw_evict_all_en.4073709938 |
|
|
Jul 13 07:20:53 PM PDT 24 |
Jul 13 07:21:29 PM PDT 24 |
48555600 ps |
| T1097 |
/workspace/coverage/default/0.flash_ctrl_intr_wr.917608292 |
|
|
Jul 13 07:18:40 PM PDT 24 |
Jul 13 07:20:29 PM PDT 24 |
9742113700 ps |
| T1098 |
/workspace/coverage/default/48.flash_ctrl_disable.873380256 |
|
|
Jul 13 07:23:42 PM PDT 24 |
Jul 13 07:24:04 PM PDT 24 |
11075200 ps |
| T1099 |
/workspace/coverage/default/3.flash_ctrl_smoke_hw.3035083570 |
|
|
Jul 13 07:19:23 PM PDT 24 |
Jul 13 07:19:59 PM PDT 24 |
18330500 ps |
| T1100 |
/workspace/coverage/default/57.flash_ctrl_connect.1650362098 |
|
|
Jul 13 07:23:46 PM PDT 24 |
Jul 13 07:24:00 PM PDT 24 |
14736300 ps |
| T1101 |
/workspace/coverage/default/7.flash_ctrl_re_evict.215863431 |
|
|
Jul 13 07:20:02 PM PDT 24 |
Jul 13 07:20:38 PM PDT 24 |
131331100 ps |
| T1102 |
/workspace/coverage/default/40.flash_ctrl_otp_reset.4264475259 |
|
|
Jul 13 07:23:24 PM PDT 24 |
Jul 13 07:25:37 PM PDT 24 |
137548300 ps |
| T1103 |
/workspace/coverage/default/39.flash_ctrl_alert_test.2906670353 |
|
|
Jul 13 07:23:15 PM PDT 24 |
Jul 13 07:23:30 PM PDT 24 |
36832200 ps |
| T1104 |
/workspace/coverage/default/0.flash_ctrl_read_word_sweep_derr.3505262239 |
|
|
Jul 13 07:18:41 PM PDT 24 |
Jul 13 07:19:26 PM PDT 24 |
22720200 ps |
| T1105 |
/workspace/coverage/default/2.flash_ctrl_disable.2270331759 |
|
|
Jul 13 07:19:10 PM PDT 24 |
Jul 13 07:19:44 PM PDT 24 |
17682000 ps |
| T1106 |
/workspace/coverage/default/6.flash_ctrl_smoke.1781866622 |
|
|
Jul 13 07:19:47 PM PDT 24 |
Jul 13 07:21:29 PM PDT 24 |
35550500 ps |
| T1107 |
/workspace/coverage/default/12.flash_ctrl_wo.3209933911 |
|
|
Jul 13 07:20:39 PM PDT 24 |
Jul 13 07:23:18 PM PDT 24 |
1792923300 ps |
| T1108 |
/workspace/coverage/default/41.flash_ctrl_hw_sec_otp.4122706837 |
|
|
Jul 13 07:23:23 PM PDT 24 |
Jul 13 07:25:26 PM PDT 24 |
3809455200 ps |
| T1109 |
/workspace/coverage/default/19.flash_ctrl_intr_rd.650902660 |
|
|
Jul 13 07:21:51 PM PDT 24 |
Jul 13 07:25:02 PM PDT 24 |
5968594800 ps |
| T179 |
/workspace/coverage/default/2.flash_ctrl_hw_rma_reset.4089952936 |
|
|
Jul 13 07:18:55 PM PDT 24 |
Jul 13 07:33:32 PM PDT 24 |
160177742900 ps |
| T1110 |
/workspace/coverage/default/3.flash_ctrl_smoke.3351472439 |
|
|
Jul 13 07:19:27 PM PDT 24 |
Jul 13 07:20:26 PM PDT 24 |
32580000 ps |
| T1111 |
/workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.4125231613 |
|
|
Jul 13 07:20:33 PM PDT 24 |
Jul 13 07:21:10 PM PDT 24 |
37703800 ps |
| T1112 |
/workspace/coverage/default/62.flash_ctrl_otp_reset.1733156464 |
|
|
Jul 13 07:23:52 PM PDT 24 |
Jul 13 07:25:43 PM PDT 24 |
324477200 ps |
| T1113 |
/workspace/coverage/default/63.flash_ctrl_otp_reset.2801155049 |
|
|
Jul 13 07:23:52 PM PDT 24 |
Jul 13 07:26:05 PM PDT 24 |
71835000 ps |
| T1114 |
/workspace/coverage/default/25.flash_ctrl_alert_test.2622386696 |
|
|
Jul 13 07:22:22 PM PDT 24 |
Jul 13 07:22:37 PM PDT 24 |
33642000 ps |
| T1115 |
/workspace/coverage/default/26.flash_ctrl_otp_reset.3148598744 |
|
|
Jul 13 07:22:26 PM PDT 24 |
Jul 13 07:24:19 PM PDT 24 |
71338800 ps |
| T1116 |
/workspace/coverage/default/44.flash_ctrl_hw_sec_otp.1702543883 |
|
|
Jul 13 07:23:27 PM PDT 24 |
Jul 13 07:24:55 PM PDT 24 |
10054631400 ps |
| T1117 |
/workspace/coverage/default/35.flash_ctrl_otp_reset.2976364917 |
|
|
Jul 13 07:23:01 PM PDT 24 |
Jul 13 07:24:52 PM PDT 24 |
77335100 ps |
| T1118 |
/workspace/coverage/default/39.flash_ctrl_intr_rd_slow_flash.2224096744 |
|
|
Jul 13 07:23:14 PM PDT 24 |
Jul 13 07:25:34 PM PDT 24 |
5884102800 ps |
| T1119 |
/workspace/coverage/default/28.flash_ctrl_connect.3266672210 |
|
|
Jul 13 07:22:35 PM PDT 24 |
Jul 13 07:22:53 PM PDT 24 |
18234600 ps |
| T1120 |
/workspace/coverage/default/1.flash_ctrl_read_word_sweep_serr.2497141065 |
|
|
Jul 13 07:18:54 PM PDT 24 |
Jul 13 07:19:36 PM PDT 24 |
56995600 ps |
| T1121 |
/workspace/coverage/default/7.flash_ctrl_intr_wr.4181456593 |
|
|
Jul 13 07:19:54 PM PDT 24 |
Jul 13 07:21:07 PM PDT 24 |
2562601600 ps |
| T1122 |
/workspace/coverage/default/7.flash_ctrl_phy_arb.2929147933 |
|
|
Jul 13 07:19:53 PM PDT 24 |
Jul 13 07:23:30 PM PDT 24 |
3638533200 ps |
| T180 |
/workspace/coverage/default/11.flash_ctrl_hw_rma_reset.2270301086 |
|
|
Jul 13 07:20:33 PM PDT 24 |
Jul 13 07:35:18 PM PDT 24 |
40128858900 ps |
| T1123 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2347181686 |
|
|
Jul 13 07:17:54 PM PDT 24 |
Jul 13 07:18:42 PM PDT 24 |
17090800 ps |
| T61 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.3419727373 |
|
|
Jul 13 07:17:59 PM PDT 24 |
Jul 13 07:18:52 PM PDT 24 |
2340649100 ps |
| T269 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.3984808258 |
|
|
Jul 13 07:18:35 PM PDT 24 |
Jul 13 07:19:10 PM PDT 24 |
42189300 ps |
| T62 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.3839390004 |
|
|
Jul 13 07:18:16 PM PDT 24 |
Jul 13 07:26:33 PM PDT 24 |
695895600 ps |
| T270 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.221587505 |
|
|
Jul 13 07:18:36 PM PDT 24 |
Jul 13 07:19:12 PM PDT 24 |
58092000 ps |
| T63 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3964828967 |
|
|
Jul 13 07:17:58 PM PDT 24 |
Jul 13 07:19:09 PM PDT 24 |
62178800 ps |
| T1124 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.1375419782 |
|
|
Jul 13 07:17:54 PM PDT 24 |
Jul 13 07:18:40 PM PDT 24 |
15714700 ps |
| T105 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.2397955146 |
|
|
Jul 13 07:18:00 PM PDT 24 |
Jul 13 07:19:22 PM PDT 24 |
404473700 ps |
| T235 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.2397265177 |
|
|
Jul 13 07:18:35 PM PDT 24 |
Jul 13 07:19:14 PM PDT 24 |
367228000 ps |
| T329 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.3442098991 |
|
|
Jul 13 07:18:04 PM PDT 24 |
Jul 13 07:18:49 PM PDT 24 |
17879200 ps |
| T106 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.2914889352 |
|
|
Jul 13 07:17:57 PM PDT 24 |
Jul 13 07:18:45 PM PDT 24 |
85931400 ps |
| T108 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.1054880882 |
|
|
Jul 13 07:17:46 PM PDT 24 |
Jul 13 07:18:33 PM PDT 24 |
319964200 ps |
| T1125 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.1534799944 |
|
|
Jul 13 07:18:21 PM PDT 24 |
Jul 13 07:19:02 PM PDT 24 |
52510100 ps |
| T264 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.3528046484 |
|
|
Jul 13 07:18:05 PM PDT 24 |
Jul 13 07:18:50 PM PDT 24 |
102572800 ps |
| T331 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.3287098278 |
|
|
Jul 13 07:18:21 PM PDT 24 |
Jul 13 07:19:00 PM PDT 24 |
20542500 ps |
| T263 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.2785864399 |
|
|
Jul 13 07:18:23 PM PDT 24 |
Jul 13 07:19:08 PM PDT 24 |
63017300 ps |
| T232 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.451867190 |
|
|
Jul 13 07:18:19 PM PDT 24 |
Jul 13 07:19:00 PM PDT 24 |
179803700 ps |
| T246 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.3262893649 |
|
|
Jul 13 07:17:52 PM PDT 24 |
Jul 13 07:18:37 PM PDT 24 |
28501200 ps |
| T240 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.1114403047 |
|
|
Jul 13 07:18:05 PM PDT 24 |
Jul 13 07:18:53 PM PDT 24 |
203236700 ps |
| T310 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.3246707684 |
|
|
Jul 13 07:18:32 PM PDT 24 |
Jul 13 07:19:14 PM PDT 24 |
146700400 ps |
| T330 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.2913113840 |
|
|
Jul 13 07:17:51 PM PDT 24 |
Jul 13 07:18:36 PM PDT 24 |
44593500 ps |
| T107 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3662879731 |
|
|
Jul 13 07:18:12 PM PDT 24 |
Jul 13 07:33:15 PM PDT 24 |
356898900 ps |
| T332 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3894871987 |
|
|
Jul 13 07:18:38 PM PDT 24 |
Jul 13 07:19:16 PM PDT 24 |
49582400 ps |
| T233 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2865694930 |
|
|
Jul 13 07:18:23 PM PDT 24 |
Jul 13 07:19:07 PM PDT 24 |
206493900 ps |
| T241 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3235579377 |
|
|
Jul 13 07:18:05 PM PDT 24 |
Jul 13 07:18:50 PM PDT 24 |
72067100 ps |
| T309 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1705930935 |
|
|
Jul 13 07:18:22 PM PDT 24 |
Jul 13 07:19:01 PM PDT 24 |
522887400 ps |
| T357 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.723832152 |
|
|
Jul 13 07:18:15 PM PDT 24 |
Jul 13 07:18:55 PM PDT 24 |
141310000 ps |
| T1126 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.3829407555 |
|
|
Jul 13 07:18:28 PM PDT 24 |
Jul 13 07:19:07 PM PDT 24 |
13722500 ps |
| T234 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.2431712713 |
|
|
Jul 13 07:17:52 PM PDT 24 |
Jul 13 07:18:38 PM PDT 24 |
95944700 ps |
| T334 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.9191234 |
|
|
Jul 13 07:18:20 PM PDT 24 |
Jul 13 07:18:59 PM PDT 24 |
15615900 ps |
| T242 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3570386523 |
|
|
Jul 13 07:18:11 PM PDT 24 |
Jul 13 07:18:53 PM PDT 24 |
133060900 ps |
| T311 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.1765188977 |
|
|
Jul 13 07:18:15 PM PDT 24 |
Jul 13 07:18:57 PM PDT 24 |
40395700 ps |
| T243 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.923880917 |
|
|
Jul 13 07:18:05 PM PDT 24 |
Jul 13 07:18:52 PM PDT 24 |
46103100 ps |
| T1127 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.243453689 |
|
|
Jul 13 07:18:21 PM PDT 24 |
Jul 13 07:19:01 PM PDT 24 |
20596600 ps |
| T1128 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.3164671035 |
|
|
Jul 13 07:18:38 PM PDT 24 |
Jul 13 07:19:16 PM PDT 24 |
14879500 ps |
| T335 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.1883442411 |
|
|
Jul 13 07:18:16 PM PDT 24 |
Jul 13 07:18:55 PM PDT 24 |
118620700 ps |
| T312 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1198224326 |
|
|
Jul 13 07:17:51 PM PDT 24 |
Jul 13 07:19:08 PM PDT 24 |
2795238700 ps |
| T358 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1602433626 |
|
|
Jul 13 07:17:50 PM PDT 24 |
Jul 13 07:18:37 PM PDT 24 |
65450500 ps |
| T261 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.540921664 |
|
|
Jul 13 07:18:01 PM PDT 24 |
Jul 13 07:25:00 PM PDT 24 |
354725500 ps |
| T1129 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.2627808523 |
|
|
Jul 13 07:18:36 PM PDT 24 |
Jul 13 07:19:12 PM PDT 24 |
52132600 ps |
| T280 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.2684159158 |
|
|
Jul 13 07:17:52 PM PDT 24 |
Jul 13 07:33:27 PM PDT 24 |
1530334600 ps |
| T1130 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.2571860472 |
|
|
Jul 13 07:17:59 PM PDT 24 |
Jul 13 07:19:17 PM PDT 24 |
44538400 ps |
| T247 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.2311990527 |
|
|
Jul 13 07:17:54 PM PDT 24 |
Jul 13 07:18:40 PM PDT 24 |
55692100 ps |
| T1131 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.1957737355 |
|
|
Jul 13 07:18:10 PM PDT 24 |
Jul 13 07:18:57 PM PDT 24 |
247720600 ps |
| T1132 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.750119058 |
|
|
Jul 13 07:17:54 PM PDT 24 |
Jul 13 07:18:42 PM PDT 24 |
13962800 ps |
| T313 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1450219438 |
|
|
Jul 13 07:18:38 PM PDT 24 |
Jul 13 07:19:36 PM PDT 24 |
215308300 ps |
| T333 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.784720391 |
|
|
Jul 13 07:18:35 PM PDT 24 |
Jul 13 07:19:10 PM PDT 24 |
22812400 ps |
| T314 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.601215144 |
|
|
Jul 13 07:17:52 PM PDT 24 |
Jul 13 07:18:42 PM PDT 24 |
440112500 ps |
| T1133 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.3848024988 |
|
|
Jul 13 07:18:07 PM PDT 24 |
Jul 13 07:18:52 PM PDT 24 |
14718300 ps |
| T276 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3145677655 |
|
|
Jul 13 07:17:55 PM PDT 24 |
Jul 13 07:26:09 PM PDT 24 |
873760700 ps |
| T248 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.2582773531 |
|
|
Jul 13 07:18:04 PM PDT 24 |
Jul 13 07:18:48 PM PDT 24 |
34156400 ps |
| T244 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.314205840 |
|
|
Jul 13 07:18:08 PM PDT 24 |
Jul 13 07:18:55 PM PDT 24 |
49845000 ps |
| T1134 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.2864271309 |
|
|
Jul 13 07:18:29 PM PDT 24 |
Jul 13 07:19:09 PM PDT 24 |
197305000 ps |
| T281 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.180623545 |
|
|
Jul 13 07:18:42 PM PDT 24 |
Jul 13 07:19:24 PM PDT 24 |
58552900 ps |
| T315 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1622922406 |
|
|
Jul 13 07:17:52 PM PDT 24 |
Jul 13 07:21:03 PM PDT 24 |
61501598200 ps |
| T272 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1350180084 |
|
|
Jul 13 07:18:16 PM PDT 24 |
Jul 13 07:18:56 PM PDT 24 |
33373300 ps |
| T275 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.273100540 |
|
|
Jul 13 07:18:12 PM PDT 24 |
Jul 13 07:26:34 PM PDT 24 |
420909700 ps |
| T1135 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1787326052 |
|
|
Jul 13 07:17:53 PM PDT 24 |
Jul 13 07:18:39 PM PDT 24 |
145153600 ps |
| T1136 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.2731865561 |
|
|
Jul 13 07:18:21 PM PDT 24 |
Jul 13 07:18:59 PM PDT 24 |
22564100 ps |
| T282 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.802760746 |
|
|
Jul 13 07:18:12 PM PDT 24 |
Jul 13 07:34:06 PM PDT 24 |
2282647400 ps |
| T285 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.3429185220 |
|
|
Jul 13 07:17:50 PM PDT 24 |
Jul 13 07:31:06 PM PDT 24 |
470658900 ps |
| T1137 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1095816759 |
|
|
Jul 13 07:17:51 PM PDT 24 |
Jul 13 07:18:41 PM PDT 24 |
74810500 ps |
| T1138 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3256446901 |
|
|
Jul 13 07:18:20 PM PDT 24 |
Jul 13 07:19:04 PM PDT 24 |
87470700 ps |
| T1139 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.985067190 |
|
|
Jul 13 07:18:34 PM PDT 24 |
Jul 13 07:19:13 PM PDT 24 |
140350200 ps |
| T316 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.151296411 |
|
|
Jul 13 07:17:56 PM PDT 24 |
Jul 13 07:19:07 PM PDT 24 |
1701414100 ps |
| T267 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.2829860222 |
|
|
Jul 13 07:18:17 PM PDT 24 |
Jul 13 07:18:58 PM PDT 24 |
44824400 ps |
| T1140 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.3129431943 |
|
|
Jul 13 07:18:13 PM PDT 24 |
Jul 13 07:18:54 PM PDT 24 |
212294700 ps |
| T1141 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.3199966174 |
|
|
Jul 13 07:18:09 PM PDT 24 |
Jul 13 07:18:54 PM PDT 24 |
58726000 ps |
| T1142 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2912778103 |
|
|
Jul 13 07:18:34 PM PDT 24 |
Jul 13 07:19:14 PM PDT 24 |
141555900 ps |
| T1143 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.153062691 |
|
|
Jul 13 07:18:34 PM PDT 24 |
Jul 13 07:19:09 PM PDT 24 |
31990600 ps |
| T1144 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.1215706226 |
|
|
Jul 13 07:18:21 PM PDT 24 |
Jul 13 07:19:02 PM PDT 24 |
72539900 ps |
| T286 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.2756175166 |
|
|
Jul 13 07:18:00 PM PDT 24 |
Jul 13 07:18:47 PM PDT 24 |
48732500 ps |
| T1145 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.7329315 |
|
|
Jul 13 07:18:13 PM PDT 24 |
Jul 13 07:18:52 PM PDT 24 |
21790900 ps |
| T268 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.1952890236 |
|
|
Jul 13 07:18:32 PM PDT 24 |
Jul 13 07:19:12 PM PDT 24 |
43091000 ps |
| T1146 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.3992801073 |
|
|
Jul 13 07:18:35 PM PDT 24 |
Jul 13 07:19:11 PM PDT 24 |
54070800 ps |
| T1147 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.4085659139 |
|
|
Jul 13 07:18:35 PM PDT 24 |
Jul 13 07:19:10 PM PDT 24 |
15785400 ps |
| T1148 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.1631401854 |
|
|
Jul 13 07:18:37 PM PDT 24 |
Jul 13 07:19:13 PM PDT 24 |
54060900 ps |
| T1149 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1240687865 |
|
|
Jul 13 07:18:36 PM PDT 24 |
Jul 13 07:19:11 PM PDT 24 |
14662700 ps |
| T1150 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.3047367422 |
|
|
Jul 13 07:18:37 PM PDT 24 |
Jul 13 07:19:14 PM PDT 24 |
17397800 ps |
| T1151 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.646882126 |
|
|
Jul 13 07:18:05 PM PDT 24 |
Jul 13 07:18:51 PM PDT 24 |
61562700 ps |
| T1152 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.2556729112 |
|
|
Jul 13 07:18:14 PM PDT 24 |
Jul 13 07:18:53 PM PDT 24 |
50026500 ps |
| T1153 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.2171393664 |
|
|
Jul 13 07:18:15 PM PDT 24 |
Jul 13 07:18:54 PM PDT 24 |
46325200 ps |
| T1154 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.5479466 |
|
|
Jul 13 07:18:15 PM PDT 24 |
Jul 13 07:19:00 PM PDT 24 |
41345500 ps |
| T1155 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.1251817326 |
|
|
Jul 13 07:18:01 PM PDT 24 |
Jul 13 07:18:48 PM PDT 24 |
24879300 ps |
| T1156 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3866825054 |
|
|
Jul 13 07:18:13 PM PDT 24 |
Jul 13 07:18:55 PM PDT 24 |
159256900 ps |
| T1157 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.3584355043 |
|
|
Jul 13 07:18:13 PM PDT 24 |
Jul 13 07:18:57 PM PDT 24 |
613264500 ps |
| T1158 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.2127533490 |
|
|
Jul 13 07:18:37 PM PDT 24 |
Jul 13 07:19:14 PM PDT 24 |
50071300 ps |
| T1159 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.1416051064 |
|
|
Jul 13 07:17:54 PM PDT 24 |
Jul 13 07:18:40 PM PDT 24 |
17131300 ps |
| T317 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2397303975 |
|
|
Jul 13 07:17:51 PM PDT 24 |
Jul 13 07:18:44 PM PDT 24 |
1167688100 ps |
| T1160 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.1036729001 |
|
|
Jul 13 07:18:13 PM PDT 24 |
Jul 13 07:18:52 PM PDT 24 |
21340600 ps |
| T348 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.4180646717 |
|
|
Jul 13 07:18:29 PM PDT 24 |
Jul 13 07:33:57 PM PDT 24 |
6420250900 ps |
| T1161 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.264666364 |
|
|
Jul 13 07:18:05 PM PDT 24 |
Jul 13 07:18:53 PM PDT 24 |
82069000 ps |
| T1162 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.3500825191 |
|
|
Jul 13 07:18:16 PM PDT 24 |
Jul 13 07:18:54 PM PDT 24 |
32585600 ps |
| T1163 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.4115605380 |
|
|
Jul 13 07:17:59 PM PDT 24 |
Jul 13 07:18:44 PM PDT 24 |
49063000 ps |
| T1164 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.1403634584 |
|
|
Jul 13 07:18:36 PM PDT 24 |
Jul 13 07:19:11 PM PDT 24 |
61259800 ps |
| T1165 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1637899740 |
|
|
Jul 13 07:18:00 PM PDT 24 |
Jul 13 07:18:47 PM PDT 24 |
12300300 ps |
| T1166 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.126947291 |
|
|
Jul 13 07:18:15 PM PDT 24 |
Jul 13 07:18:57 PM PDT 24 |
130540100 ps |
| T1167 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.3156206176 |
|
|
Jul 13 07:18:33 PM PDT 24 |
Jul 13 07:19:11 PM PDT 24 |
11310000 ps |
| T1168 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.3595187840 |
|
|
Jul 13 07:18:36 PM PDT 24 |
Jul 13 07:19:12 PM PDT 24 |
18445200 ps |
| T271 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3006209443 |
|
|
Jul 13 07:18:38 PM PDT 24 |
Jul 13 07:34:15 PM PDT 24 |
2890539000 ps |
| T1169 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1335288758 |
|
|
Jul 13 07:18:42 PM PDT 24 |
Jul 13 07:19:19 PM PDT 24 |
13787000 ps |
| T1170 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.4184204369 |
|
|
Jul 13 07:18:05 PM PDT 24 |
Jul 13 07:18:48 PM PDT 24 |
14227600 ps |
| T265 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1023500238 |
|
|
Jul 13 07:18:00 PM PDT 24 |
Jul 13 07:18:51 PM PDT 24 |
228656100 ps |
| T1171 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1314359641 |
|
|
Jul 13 07:18:11 PM PDT 24 |
Jul 13 07:18:54 PM PDT 24 |
12748300 ps |
| T1172 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.244533329 |
|
|
Jul 13 07:18:14 PM PDT 24 |
Jul 13 07:18:57 PM PDT 24 |
123131700 ps |
| T1173 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.3506262997 |
|
|
Jul 13 07:17:52 PM PDT 24 |
Jul 13 07:18:39 PM PDT 24 |
13977900 ps |
| T249 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3359353513 |
|
|
Jul 13 07:17:52 PM PDT 24 |
Jul 13 07:18:36 PM PDT 24 |
46229500 ps |
| T1174 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.132790792 |
|
|
Jul 13 07:18:28 PM PDT 24 |
Jul 13 07:19:07 PM PDT 24 |
30081400 ps |
| T1175 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.786348521 |
|
|
Jul 13 07:18:13 PM PDT 24 |
Jul 13 07:19:00 PM PDT 24 |
339372500 ps |
| T1176 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.1459708366 |
|
|
Jul 13 07:18:34 PM PDT 24 |
Jul 13 07:19:10 PM PDT 24 |
29865100 ps |
| T1177 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.2348825338 |
|
|
Jul 13 07:17:52 PM PDT 24 |
Jul 13 07:18:56 PM PDT 24 |
1020015400 ps |
| T1178 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.829728808 |
|
|
Jul 13 07:18:37 PM PDT 24 |
Jul 13 07:19:13 PM PDT 24 |
32393500 ps |
| T1179 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2676137333 |
|
|
Jul 13 07:18:18 PM PDT 24 |
Jul 13 07:18:58 PM PDT 24 |
17950000 ps |
| T1180 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.1468393572 |
|
|
Jul 13 07:18:36 PM PDT 24 |
Jul 13 07:19:12 PM PDT 24 |
53289400 ps |
| T1181 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.746923322 |
|
|
Jul 13 07:17:53 PM PDT 24 |
Jul 13 07:18:56 PM PDT 24 |
210640800 ps |
| T1182 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.3642961733 |
|
|
Jul 13 07:18:05 PM PDT 24 |
Jul 13 07:18:51 PM PDT 24 |
11666700 ps |
| T1183 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2131047614 |
|
|
Jul 13 07:18:06 PM PDT 24 |
Jul 13 07:18:54 PM PDT 24 |
132099700 ps |
| T1184 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.1434024837 |
|
|
Jul 13 07:18:41 PM PDT 24 |
Jul 13 07:19:17 PM PDT 24 |
15101900 ps |
| T1185 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.4221709403 |
|
|
Jul 13 07:17:54 PM PDT 24 |
Jul 13 07:19:29 PM PDT 24 |
2528491100 ps |
| T266 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1951255582 |
|
|
Jul 13 07:18:26 PM PDT 24 |
Jul 13 07:19:10 PM PDT 24 |
182174200 ps |
| T1186 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.912857630 |
|
|
Jul 13 07:18:42 PM PDT 24 |
Jul 13 07:19:19 PM PDT 24 |
93405400 ps |
| T283 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.2886495478 |
|
|
Jul 13 07:17:52 PM PDT 24 |
Jul 13 07:33:20 PM PDT 24 |
1460275800 ps |
| T1187 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.1721814779 |
|
|
Jul 13 07:17:54 PM PDT 24 |
Jul 13 07:18:40 PM PDT 24 |
71625700 ps |
| T1188 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.4007328139 |
|
|
Jul 13 07:17:52 PM PDT 24 |
Jul 13 07:18:38 PM PDT 24 |
24604700 ps |
| T1189 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.3175906569 |
|
|
Jul 13 07:18:06 PM PDT 24 |
Jul 13 07:18:53 PM PDT 24 |
11386700 ps |
| T278 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.760560025 |
|
|
Jul 13 07:17:52 PM PDT 24 |
Jul 13 07:18:41 PM PDT 24 |
42752200 ps |
| T1190 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.3835999561 |
|
|
Jul 13 07:18:04 PM PDT 24 |
Jul 13 07:18:52 PM PDT 24 |
152772100 ps |
| T1191 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1593486832 |
|
|
Jul 13 07:18:33 PM PDT 24 |
Jul 13 07:19:09 PM PDT 24 |
26447900 ps |
| T284 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.2990968997 |
|
|
Jul 13 07:18:22 PM PDT 24 |
Jul 13 07:26:28 PM PDT 24 |
6768861000 ps |
| T1192 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.1248162010 |
|
|
Jul 13 07:18:01 PM PDT 24 |
Jul 13 07:18:47 PM PDT 24 |
147930600 ps |
| T1193 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.539925479 |
|
|
Jul 13 07:18:12 PM PDT 24 |
Jul 13 07:18:52 PM PDT 24 |
14225100 ps |
| T318 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.321621364 |
|
|
Jul 13 07:18:00 PM PDT 24 |
Jul 13 07:18:49 PM PDT 24 |
107762800 ps |
| T1194 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2608567334 |
|
|
Jul 13 07:18:00 PM PDT 24 |
Jul 13 07:18:46 PM PDT 24 |
56632600 ps |
| T1195 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.1515461102 |
|
|
Jul 13 07:18:33 PM PDT 24 |
Jul 13 07:19:09 PM PDT 24 |
28545800 ps |
| T1196 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.995754787 |
|
|
Jul 13 07:17:47 PM PDT 24 |
Jul 13 07:18:31 PM PDT 24 |
16478900 ps |
| T1197 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1187518701 |
|
|
Jul 13 07:17:55 PM PDT 24 |
Jul 13 07:18:42 PM PDT 24 |
50442300 ps |
| T319 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.1980398619 |
|
|
Jul 13 07:17:52 PM PDT 24 |
Jul 13 07:19:33 PM PDT 24 |
1717970300 ps |
| T279 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2305499108 |
|
|
Jul 13 07:17:52 PM PDT 24 |
Jul 13 07:18:43 PM PDT 24 |
115978500 ps |
| T351 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.152305095 |
|
|
Jul 13 07:18:36 PM PDT 24 |
Jul 13 07:34:24 PM PDT 24 |
2964509600 ps |
| T273 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.3312685852 |
|
|
Jul 13 07:18:01 PM PDT 24 |
Jul 13 07:18:53 PM PDT 24 |
238485000 ps |
| T349 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.3445461078 |
|
|
Jul 13 07:18:05 PM PDT 24 |
Jul 13 07:26:23 PM PDT 24 |
433469800 ps |
| T1198 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.99380774 |
|
|
Jul 13 07:18:34 PM PDT 24 |
Jul 13 07:19:09 PM PDT 24 |
32447600 ps |
| T1199 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3329858895 |
|
|
Jul 13 07:18:35 PM PDT 24 |
Jul 13 07:19:10 PM PDT 24 |
18747500 ps |
| T1200 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.3699243262 |
|
|
Jul 13 07:18:27 PM PDT 24 |
Jul 13 07:19:05 PM PDT 24 |
774584900 ps |
| T1201 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.916215599 |
|
|
Jul 13 07:18:38 PM PDT 24 |
Jul 13 07:19:14 PM PDT 24 |
15580500 ps |
| T1202 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2597292997 |
|
|
Jul 13 07:18:27 PM PDT 24 |
Jul 13 07:19:12 PM PDT 24 |
1081699400 ps |
| T1203 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.82067728 |
|
|
Jul 13 07:18:38 PM PDT 24 |
Jul 13 07:19:20 PM PDT 24 |
98076800 ps |
| T354 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2580439059 |
|
|
Jul 13 07:18:05 PM PDT 24 |
Jul 13 07:26:13 PM PDT 24 |
1887493500 ps |
| T287 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.246316864 |
|
|
Jul 13 07:18:06 PM PDT 24 |
Jul 13 07:33:45 PM PDT 24 |
1439617000 ps |
| T1204 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.4281890861 |
|
|
Jul 13 07:18:34 PM PDT 24 |
Jul 13 07:19:08 PM PDT 24 |
25320400 ps |
| T1205 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.950929133 |
|
|
Jul 13 07:18:19 PM PDT 24 |
Jul 13 07:19:03 PM PDT 24 |
384562600 ps |
| T1206 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.1988248432 |
|
|
Jul 13 07:18:15 PM PDT 24 |
Jul 13 07:18:54 PM PDT 24 |
14821600 ps |
| T1207 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.1227502125 |
|
|
Jul 13 07:17:46 PM PDT 24 |
Jul 13 07:18:33 PM PDT 24 |
42416100 ps |
| T1208 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1944557978 |
|
|
Jul 13 07:18:00 PM PDT 24 |
Jul 13 07:18:45 PM PDT 24 |
149746700 ps |
| T347 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2454996085 |
|
|
Jul 13 07:18:18 PM PDT 24 |
Jul 13 07:19:04 PM PDT 24 |
58947700 ps |
| T1209 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.2903143987 |
|
|
Jul 13 07:18:01 PM PDT 24 |
Jul 13 07:18:49 PM PDT 24 |
221781600 ps |
| T1210 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.113852727 |
|
|
Jul 13 07:18:35 PM PDT 24 |
Jul 13 07:19:10 PM PDT 24 |
65977000 ps |
| T1211 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.5823736 |
|
|
Jul 13 07:18:38 PM PDT 24 |
Jul 13 07:19:14 PM PDT 24 |
30382700 ps |
| T1212 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.2506487393 |
|
|
Jul 13 07:17:54 PM PDT 24 |
Jul 13 07:18:40 PM PDT 24 |
44467700 ps |
| T1213 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.965570465 |
|
|
Jul 13 07:18:06 PM PDT 24 |
Jul 13 07:18:57 PM PDT 24 |
797328200 ps |
| T1214 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.4245604078 |
|
|
Jul 13 07:18:23 PM PDT 24 |
Jul 13 07:19:06 PM PDT 24 |
65289700 ps |
| T352 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.1254178814 |
|
|
Jul 13 07:18:08 PM PDT 24 |
Jul 13 07:33:48 PM PDT 24 |
1291674400 ps |
| T1215 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.2230072826 |
|
|
Jul 13 07:17:55 PM PDT 24 |
Jul 13 07:18:43 PM PDT 24 |
667030900 ps |
| T1216 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.1117789896 |
|
|
Jul 13 07:18:06 PM PDT 24 |
Jul 13 07:18:49 PM PDT 24 |
63663800 ps |
| T1217 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.2456326569 |
|
|
Jul 13 07:18:00 PM PDT 24 |
Jul 13 07:18:46 PM PDT 24 |
55800300 ps |
| T1218 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.2600467687 |
|
|
Jul 13 07:17:54 PM PDT 24 |
Jul 13 07:18:40 PM PDT 24 |
17886800 ps |
| T1219 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.3415938742 |
|
|
Jul 13 07:18:07 PM PDT 24 |
Jul 13 07:18:50 PM PDT 24 |
19804300 ps |
| T1220 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2047722369 |
|
|
Jul 13 07:18:37 PM PDT 24 |
Jul 13 07:19:18 PM PDT 24 |
95230900 ps |
| T1221 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.1298381718 |
|
|
Jul 13 07:18:05 PM PDT 24 |
Jul 13 07:18:50 PM PDT 24 |
45025600 ps |
| T1222 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.1218135300 |
|
|
Jul 13 07:18:34 PM PDT 24 |
Jul 13 07:19:09 PM PDT 24 |
33038800 ps |
| T1223 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.1243102303 |
|
|
Jul 13 07:18:26 PM PDT 24 |
Jul 13 07:19:03 PM PDT 24 |
18602900 ps |
| T1224 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3063240168 |
|
|
Jul 13 07:17:49 PM PDT 24 |
Jul 13 07:19:08 PM PDT 24 |
24550300 ps |
| T1225 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.1138234635 |
|
|
Jul 13 07:18:37 PM PDT 24 |
Jul 13 07:19:14 PM PDT 24 |
16241600 ps |
| T1226 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.894461892 |
|
|
Jul 13 07:17:52 PM PDT 24 |
Jul 13 07:18:36 PM PDT 24 |
35482100 ps |
| T1227 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.163320436 |
|
|
Jul 13 07:18:36 PM PDT 24 |
Jul 13 07:19:17 PM PDT 24 |
54989400 ps |
| T1228 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.1688352351 |
|
|
Jul 13 07:18:26 PM PDT 24 |
Jul 13 07:26:30 PM PDT 24 |
365019100 ps |
| T277 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3863862783 |
|
|
Jul 13 07:18:04 PM PDT 24 |
Jul 13 07:18:54 PM PDT 24 |
68541700 ps |
| T288 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.643815331 |
|
|
Jul 13 07:18:18 PM PDT 24 |
Jul 13 07:19:03 PM PDT 24 |
235465600 ps |
| T1229 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2236350378 |
|
|
Jul 13 07:18:37 PM PDT 24 |
Jul 13 07:19:13 PM PDT 24 |
41878300 ps |
| T1230 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.260567122 |
|
|
Jul 13 07:18:00 PM PDT 24 |
Jul 13 07:18:48 PM PDT 24 |
139390000 ps |
| T274 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.4155242865 |
|
|
Jul 13 07:18:14 PM PDT 24 |
Jul 13 07:19:00 PM PDT 24 |
169609700 ps |
| T1231 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.2551947359 |
|
|
Jul 13 07:18:38 PM PDT 24 |
Jul 13 07:19:14 PM PDT 24 |
188039300 ps |
| T1232 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.3348447559 |
|
|
Jul 13 07:18:27 PM PDT 24 |
Jul 13 07:19:05 PM PDT 24 |
78887300 ps |
| T1233 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.1083273971 |
|
|
Jul 13 07:17:53 PM PDT 24 |
Jul 13 07:19:12 PM PDT 24 |
183191300 ps |
| T1234 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.2491466580 |
|
|
Jul 13 07:18:00 PM PDT 24 |
Jul 13 07:19:33 PM PDT 24 |
635957700 ps |
| T1235 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.3603889173 |
|
|
Jul 13 07:18:13 PM PDT 24 |
Jul 13 07:18:55 PM PDT 24 |
11739800 ps |
| T353 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.1338078816 |
|
|
Jul 13 07:18:13 PM PDT 24 |
Jul 13 07:26:26 PM PDT 24 |
683881500 ps |
| T1236 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.2717526869 |
|
|
Jul 13 07:17:48 PM PDT 24 |
Jul 13 07:18:33 PM PDT 24 |
16488100 ps |
| T1237 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.2056075388 |
|
|
Jul 13 07:18:07 PM PDT 24 |
Jul 13 07:18:52 PM PDT 24 |
21570100 ps |
| T1238 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.3570807490 |
|
|
Jul 13 07:18:34 PM PDT 24 |
Jul 13 07:19:26 PM PDT 24 |
61790000 ps |
| T1239 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1458306375 |
|
|
Jul 13 07:18:18 PM PDT 24 |
Jul 13 07:19:01 PM PDT 24 |
135800500 ps |
| T1240 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.1744305750 |
|
|
Jul 13 07:18:24 PM PDT 24 |
Jul 13 07:19:09 PM PDT 24 |
622559600 ps |
| T1241 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.41583658 |
|
|
Jul 13 07:18:12 PM PDT 24 |
Jul 13 07:18:52 PM PDT 24 |
25248700 ps |
| T1242 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.2800943420 |
|
|
Jul 13 07:18:08 PM PDT 24 |
Jul 13 07:18:56 PM PDT 24 |
205250700 ps |
| T1243 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.3444178122 |
|
|
Jul 13 07:17:49 PM PDT 24 |
Jul 13 07:18:37 PM PDT 24 |
40613400 ps |
| T1244 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.3791146547 |
|
|
Jul 13 07:18:42 PM PDT 24 |
Jul 13 07:19:20 PM PDT 24 |
33675000 ps |
| T1245 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.659703423 |
|
|
Jul 13 07:18:20 PM PDT 24 |
Jul 13 07:19:01 PM PDT 24 |
19737900 ps |
| T1246 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.4026062417 |
|
|
Jul 13 07:18:07 PM PDT 24 |
Jul 13 07:19:07 PM PDT 24 |
49098400 ps |
| T1247 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2601401074 |
|
|
Jul 13 07:18:16 PM PDT 24 |
Jul 13 07:18:55 PM PDT 24 |
113070600 ps |
| T1248 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2262157787 |
|
|
Jul 13 07:18:12 PM PDT 24 |
Jul 13 07:18:52 PM PDT 24 |
44009400 ps |
| T1249 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.3631880557 |
|
|
Jul 13 07:18:18 PM PDT 24 |
Jul 13 07:18:58 PM PDT 24 |
14489700 ps |
| T1250 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.959059276 |
|
|
Jul 13 07:17:58 PM PDT 24 |
Jul 13 07:18:48 PM PDT 24 |
177371700 ps |
| T350 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3822132516 |
|
|
Jul 13 07:17:59 PM PDT 24 |
Jul 13 07:24:59 PM PDT 24 |
225582200 ps |
| T1251 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.234131220 |
|
|
Jul 13 07:17:59 PM PDT 24 |
Jul 13 07:18:47 PM PDT 24 |
68584300 ps |