Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	498935	1		T1	1		T2	1		T3	1559
all_values[1]	498935	1		T1	1		T2	1		T3	1559
all_values[2]	498935	1		T1	1		T2	1		T3	1559
all_values[3]	498935	1		T1	1		T2	1		T3	1559
all_values[4]	498935	1		T1	1		T2	1		T3	1559
all_values[5]	498935	1		T1	1		T2	1		T3	1559

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1004057	1		T1	6		T2	6		T3	3118
auto[1]	1989553	1		T3	6236		T27	13576		T30	76276

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1468771	1		T1	4		T2	4		T3	4678
auto[1]	1524839	1		T1	2		T2	2		T3	4676

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	498766	1		T1	1		T2	1		T3	1559
all_values[0]	auto[1]	auto[1]	169	1		T260	5		T261	3		T262	5
all_values[1]	auto[0]	auto[1]	498763	1		T1	1		T2	1		T3	1559
all_values[1]	auto[1]	auto[1]	172	1		T260	6		T261	3		T262	2
all_values[2]	auto[0]	auto[0]	1572	1		T1	1		T2	1		T4	2
all_values[2]	auto[0]	auto[1]	64	1		T260	2		T261	1		T262	2
all_values[2]	auto[1]	auto[0]	497242	1		T3	1559		T27	3394		T30	19069
all_values[2]	auto[1]	auto[1]	57	1		T260	2		T261	1		T325	2
all_values[3]	auto[0]	auto[0]	1579	1		T1	1		T2	1		T4	2
all_values[3]	auto[0]	auto[1]	65	1		T261	3		T325	2		T326	1
all_values[3]	auto[1]	auto[0]	99132	1		T3	1559		T27	1697		T29	1658
all_values[3]	auto[1]	auto[1]	398159	1		T27	1697		T30	19069		T24	1711
all_values[4]	auto[0]	auto[0]	1106	1		T1	1		T2	1		T4	1
all_values[4]	auto[0]	auto[1]	500	1		T4	1		T5	1		T6	1
all_values[4]	auto[1]	auto[0]	369374	1		T3	1		T27	1697		T30	18316
all_values[4]	auto[1]	auto[1]	127955	1		T3	1558		T27	1697		T30	753
all_values[5]	auto[0]	auto[0]	1537	1		T1	1		T2	1		T4	2
all_values[5]	auto[0]	auto[1]	105	1		T7	1		T8	1		T40	1
all_values[5]	auto[1]	auto[0]	497229	1		T3	1559		T27	3394		T30	19069
all_values[5]	auto[1]	auto[1]	64	1		T260	2		T261	3		T262	1