Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	1	15	93.75

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	1	15	93.75	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	254032	1		T3	677		T4	100		T5	1376
auto[FlashEraseBank]	279569	1		T3	881		T4	1321		T5	1986

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	279349	1		T4	672		T5	1461		T7	1092
auto[FlashOpProgram]	234292	1		T3	1558		T4	708		T5	1901
auto[FlashOpErase]	15960	1		T4	41		T34	5		T58	22
auto[FlashOpInvalid]	4000	1		T83	200		T149	200		T277	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	279349	1		T4	672		T5	1461		T7	1092
op[FlashOpProgram]	234292	1		T3	1558		T4	708		T5	1901
op[FlashOpErase]	15960	1		T4	41		T34	5		T58	22
read_erase_read	601	1		T4	4		T34	1		T58	7
read_prog_read	875	1		T4	4		T5	6		T23	2

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	393100	1		T3	1350		T4	97		T5	2890
auto[FlashPartInfo]	137146	1		T3	202		T4	1324		T5	455
auto[FlashPartInfo1]	684	1		T5	1		T7	1		T8	4
auto[FlashPartInfo2]	2671	1		T3	6		T5	16		T7	6

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for op_part_cross

Uncovered bins

part_cp	op_cp	COUNT	AT LEAST	NUMBER
[auto[FlashPartInfo1]]	[auto[FlashOpInvalid]]	0	1	1

Covered bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	209059	1		T4	30		T5	1229		T7	804
auto[FlashPartData]	auto[FlashOpProgram]	176519	1		T3	1350		T4	35		T5	1661
auto[FlashPartData]	auto[FlashOpErase]	3600	1		T4	32		T58	22		T59	4
auto[FlashPartData]	auto[FlashOpInvalid]	3922	1		T83	190		T149	192		T277	198
auto[FlashPartInfo]	auto[FlashOpRead]	68050	1		T4	642		T5	223		T7	281
auto[FlashPartInfo]	auto[FlashOpProgram]	56700	1		T3	202		T4	673		T5	232
auto[FlashPartInfo]	auto[FlashOpErase]	12324	1		T4	9		T34	5		T44	259
auto[FlashPartInfo]	auto[FlashOpInvalid]	72	1		T83	10		T149	8		T277	2
auto[FlashPartInfo1]	auto[FlashOpRead]	519	1		T5	1		T7	1		T8	4
auto[FlashPartInfo1]	auto[FlashOpProgram]	164	1		T140	32		T131	32		T133	1
auto[FlashPartInfo1]	auto[FlashOpErase]	1	1		T132	1		-	-		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1721	1		T5	8		T7	6		T8	11
auto[FlashPartInfo2]	auto[FlashOpProgram]	909	1		T3	6		T5	8		T42	6
auto[FlashPartInfo2]	auto[FlashOpErase]	35	1		T128	2		T147	1		T129	2
auto[FlashPartInfo2]	auto[FlashOpInvalid]	6	1		T343	4		T344	2		-	-