Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31549	1		T4	12		T58	8		T44	524
auto[1]	25	1		T32	1		T68	1		T122	2
auto[2]	52	1		T214	1		T113	2		T147	2
auto[3]	293	1		T28	1		T216	1		T288	17

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7982	1		T4	3		T58	2		T44	131
evic_idx[1]	7979	1		T4	3		T58	2		T44	131
evic_idx[2]	7977	1		T4	3		T58	2		T44	131
evic_idx[3]	7981	1		T4	3		T58	2		T44	131

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	30979	1		T44	524		T49	104		T45	688
evic_op[2]	344	1		T35	4		T59	1		T28	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7668	1		T44	131		T49	26		T45	172
evic_idx[0]	evic_op[1]	auto[1]	5	1		T122	1		T322	2		T398	2
evic_idx[0]	evic_op[1]	auto[2]	7	1		T399	3		T400	1		T401	1
evic_idx[0]	evic_op[1]	auto[3]	67	1		T288	5		T122	1		T402	5
evic_idx[0]	evic_op[2]	auto[0]	72	1		T35	1		T59	1		T65	4
evic_idx[0]	evic_op[2]	auto[1]	2	1		T279	1		T403	1		-	-
evic_idx[0]	evic_op[2]	auto[2]	3	1		T214	1		T113	1		T404	1
evic_idx[0]	evic_op[2]	auto[3]	9	1		T28	1		T158	1		T211	1
evic_idx[1]	evic_op[1]	auto[0]	7671	1		T44	131		T49	26		T45	172
evic_idx[1]	evic_op[1]	auto[1]	3	1		T322	2		T398	1		-	-
evic_idx[1]	evic_op[1]	auto[2]	8	1		T399	3		T400	1		T401	3
evic_idx[1]	evic_op[1]	auto[3]	66	1		T288	4		T122	2		T402	4
evic_idx[1]	evic_op[2]	auto[0]	70	1		T35	1		T65	4		T405	1
evic_idx[1]	evic_op[2]	auto[1]	1	1		T403	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[2]	4	1		T211	1		T279	1		T406	1
evic_idx[1]	evic_op[2]	auto[3]	7	1		T407	1		T408	1		T409	1
evic_idx[2]	evic_op[1]	auto[0]	7670	1		T44	131		T49	26		T45	172
evic_idx[2]	evic_op[1]	auto[1]	3	1		T399	1		T322	1		T398	1
evic_idx[2]	evic_op[1]	auto[2]	11	1		T147	2		T399	3		T400	1
evic_idx[2]	evic_op[1]	auto[3]	56	1		T288	4		T122	1		T399	1
evic_idx[2]	evic_op[2]	auto[0]	74	1		T35	1		T25	1		T65	4
evic_idx[2]	evic_op[2]	auto[1]	2	1		T32	1		T68	1		-	-
evic_idx[2]	evic_op[2]	auto[2]	2	1		T113	1		T158	1		-	-
evic_idx[2]	evic_op[2]	auto[3]	10	1		T166	1		T209	1		T410	1
evic_idx[3]	evic_op[1]	auto[0]	7669	1		T44	131		T49	26		T45	172
evic_idx[3]	evic_op[1]	auto[1]	5	1		T122	1		T399	1		T322	2
evic_idx[3]	evic_op[1]	auto[2]	6	1		T399	1		T322	1		T400	1
evic_idx[3]	evic_op[1]	auto[3]	64	1		T288	4		T122	1		T399	1
evic_idx[3]	evic_op[2]	auto[0]	67	1		T35	1		T65	4		T245	1
evic_idx[3]	evic_op[2]	auto[1]	4	1		T411	1		T412	1		T403	1
evic_idx[3]	evic_op[2]	auto[2]	3	1		T279	1		T404	2		-	-
evic_idx[3]	evic_op[2]	auto[3]	14	1		T216	1		T413	1		T414	1