Summary for Variable instr_type_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for instr_type_cp
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
others |
4193 |
1 |
|
T52 |
99 |
|
T53 |
106 |
|
T54 |
190 |
instr_types[0] |
5487 |
1 |
|
T52 |
189 |
|
T53 |
237 |
|
T54 |
256 |
instr_types[1] |
4176612 |
1 |
|
T5 |
41477 |
|
T7 |
16360 |
|
T8 |
16034 |
Summary for Variable key_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for key_cp
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4184237 |
1 |
|
T5 |
41477 |
|
T7 |
16360 |
|
T8 |
16034 |
auto[1] |
2055 |
1 |
|
T52 |
140 |
|
T53 |
208 |
|
T54 |
286 |
Summary for Cross key_instr_cross
Samples crossed: key_cp instr_type_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins for key_instr_cross
Bins
key_cp | instr_type_cp | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
others |
3839 |
1 |
|
T52 |
62 |
|
T53 |
106 |
|
T54 |
142 |
auto[0] |
instr_types[0] |
4612 |
1 |
|
T52 |
141 |
|
T53 |
147 |
|
T54 |
172 |
auto[0] |
instr_types[1] |
4175786 |
1 |
|
T5 |
41477 |
|
T7 |
16360 |
|
T8 |
16034 |
auto[1] |
others |
354 |
1 |
|
T52 |
37 |
|
T54 |
48 |
|
T55 |
43 |
auto[1] |
instr_types[0] |
875 |
1 |
|
T52 |
48 |
|
T53 |
90 |
|
T54 |
84 |
auto[1] |
instr_types[1] |
826 |
1 |
|
T52 |
55 |
|
T53 |
118 |
|
T54 |
154 |