Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

---

Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	74155	1		T30	7774		T139	15617		T332	15581
rd_lvl[2]	58950	1		T30	4274		T139	11215		T333	1412
rd_lvl[3]	16865	1		T334	729		T136	4469		T333	584
rd_lvl[4]	37327	1		T314	1547		T334	2081		T136	4251
rd_lvl[5]	30385	1		T314	548		T334	104		T333	328
rd_lvl[6]	21880	1		T314	15		T334	1244		T333	260
rd_lvl[7]	17065	1		T314	43		T334	1537		T212	733
rd_lvl[8]	16690	1		T314	33		T334	945		T212	457
rd_lvl[9]	9745	1		T111	427		T37	219		T285	552
rd_lvl[10]	14429	1		T27	1255		T111	1217		T314	1
rd_lvl[11]	2474	1		T27	442		T36	259		T314	1
rd_lvl[12]	10678	1		T24	1328		T219	1384		T36	274
rd_lvl[13]	4268	1		T24	383		T36	1		T335	280
rd_lvl[14]	9189	1		T36	16		T228	1472		T38	963
rd_lvl[15]	3605	1		T228	346		T336	376		T337	208