Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	498935	1		T1	1		T2	1		T3	1559
all_pins[1]	498935	1		T1	1		T2	1		T3	1559
all_pins[2]	498935	1		T1	1		T2	1		T3	1559
all_pins[3]	498935	1		T1	1		T2	1		T3	1559
all_pins[4]	498935	1		T1	1		T2	1		T3	1559
all_pins[5]	498935	1		T1	1		T2	1		T3	1559

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2521797	1		T1	6		T2	6		T3	7796
values[0x1]	471813	1		T3	1558		T27	3394		T30	13257
transitions[0x0=>0x1]	428931	1		T3	1558		T27	3394		T30	12048
transitions[0x1=>0x0]	428910	1		T3	1558		T27	3394		T30	12048

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	498766	1		T1	1		T2	1		T3	1559
all_pins[0]	values[0x1]	169	1		T260	5		T261	3		T262	5
all_pins[0]	transitions[0x0=>0x1]	85	1		T260	1		T261	1		T262	5
all_pins[0]	transitions[0x1=>0x0]	88	1		T260	2		T261	1		T262	2
all_pins[1]	values[0x0]	498763	1		T1	1		T2	1		T3	1559
all_pins[1]	values[0x1]	172	1		T260	6		T261	3		T262	2
all_pins[1]	transitions[0x0=>0x1]	139	1		T260	5		T261	2		T262	2
all_pins[1]	transitions[0x1=>0x0]	1436	1		T337	103		T345	244		T346	4
all_pins[2]	values[0x0]	497466	1		T1	1		T2	1		T3	1559
all_pins[2]	values[0x1]	1469	1		T337	103		T345	244		T346	4
all_pins[2]	transitions[0x0=>0x1]	40	1		T260	1		T325	1		T326	1
all_pins[2]	transitions[0x1=>0x0]	327752	1		T27	1697		T30	12048		T24	1711
all_pins[3]	values[0x0]	169754	1		T1	1		T2	1		T3	1559
all_pins[3]	values[0x1]	329181	1		T27	1697		T30	12048		T24	1711
all_pins[3]	transitions[0x0=>0x1]	287902	1		T27	1697		T30	10839		T24	1711
all_pins[3]	transitions[0x1=>0x0]	99479	1		T3	1558		T27	1697		T29	1657
all_pins[4]	values[0x0]	358177	1		T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	140758	1		T3	1558		T27	1697		T30	1209
all_pins[4]	transitions[0x0=>0x1]	140736	1		T3	1558		T27	1697		T30	1209
all_pins[4]	transitions[0x1=>0x0]	42	1		T260	2		T261	2		T262	1
all_pins[5]	values[0x0]	498871	1		T1	1		T2	1		T3	1559
all_pins[5]	values[0x1]	64	1		T260	2		T261	3		T262	1
all_pins[5]	transitions[0x0=>0x1]	29	1		T261	2		T325	2		T331	1
all_pins[5]	transitions[0x1=>0x0]	113	1		T260	2		T261	2		T262	3