Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	369453	1		T1	1		T2	1		T3	1
all_values[1]	369453	1		T1	1		T2	1		T3	1
all_values[2]	369453	1		T1	1		T2	1		T3	1
all_values[3]	369453	1		T1	1		T2	1		T3	1
all_values[4]	369453	1		T1	1		T2	1		T3	1
all_values[5]	369453	1		T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	745232	1		T1	6		T2	6		T3	6
auto[1]	1471486	1		T5	17564		T29	6400		T38	12040

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1087722	1		T1	4		T2	4		T3	4
auto[1]	1128996	1		T1	2		T2	2		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	369312	1		T1	1		T2	1		T3	1
all_values[0]	auto[1]	auto[1]	141	1		T263	6		T264	1		T336	1
all_values[1]	auto[0]	auto[1]	369307	1		T1	1		T2	1		T3	1
all_values[1]	auto[1]	auto[1]	146	1		T263	6		T264	3		T336	1
all_values[2]	auto[0]	auto[0]	1594	1		T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	60	1		T264	2		T337	1		T338	1
all_values[2]	auto[1]	auto[0]	367733	1		T5	4391		T29	1600		T38	3010
all_values[2]	auto[1]	auto[1]	66	1		T263	2		T264	3		T336	3
all_values[3]	auto[0]	auto[0]	1600	1		T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	62	1		T263	2		T264	2		T336	1
all_values[3]	auto[1]	auto[0]	87093	1		T5	1086		T29	1600		T38	1505
all_values[3]	auto[1]	auto[1]	280698	1		T5	3305		T38	1505		T39	44049
all_values[4]	auto[0]	auto[0]	1132	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	502	1		T19	1		T6	1		T44	1
all_values[4]	auto[1]	auto[0]	259285	1		T5	3282		T29	1		T38	1505
all_values[4]	auto[1]	auto[1]	108534	1		T5	1109		T29	1599		T38	1505
all_values[5]	auto[0]	auto[0]	1557	1		T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	106	1		T41	1		T42	1		T43	1
all_values[5]	auto[1]	auto[0]	367728	1		T5	4391		T29	1600		T38	3010
all_values[5]	auto[1]	auto[1]	62	1		T263	2		T264	2		T337	2