Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	251506	1		T3	1460		T4	144		T18	5
auto[FlashEraseBank]	280943	1		T18	1		T5	545		T21	7

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	267307	1		T3	726		T4	42		T19	12
auto[FlashOpProgram]	245788	1		T3	367		T4	61		T18	6
auto[FlashOpErase]	15354	1		T3	367		T4	41		T19	12
auto[FlashOpInvalid]	4000	1		T81	200		T212	200		T299	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	267307	1		T3	726		T4	42		T19	12
op[FlashOpProgram]	245788	1		T3	367		T4	61		T18	6
op[FlashOpErase]	15354	1		T3	367		T4	41		T19	12
read_erase_read	520	1		T27	10		T44	2		T143	12
read_prog_read	974	1		T21	1		T26	1		T6	5

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	391948	1		T4	144		T18	1		T5	952
auto[FlashPartInfo]	136979	1		T3	1460		T18	5		T19	216
auto[FlashPartInfo1]	873	1		T6	2		T44	12		T58	3
auto[FlashPartInfo2]	2649	1		T5	38		T6	14		T27	1

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	196268	1		T4	42		T5	952		T21	1
auto[FlashPartData]	auto[FlashOpProgram]	188124	1		T4	61		T18	1		T26	1
auto[FlashPartData]	auto[FlashOpErase]	3636	1		T4	41		T27	11		T44	7
auto[FlashPartData]	auto[FlashOpInvalid]	3920	1		T81	196		T212	198		T299	196
auto[FlashPartInfo]	auto[FlashOpRead]	68610	1		T3	726		T19	12		T5	119
auto[FlashPartInfo]	auto[FlashOpProgram]	56604	1		T3	367		T18	5		T19	192
auto[FlashPartInfo]	auto[FlashOpErase]	11695	1		T3	367		T19	12		T27	4
auto[FlashPartInfo]	auto[FlashOpInvalid]	70	1		T81	4		T212	2		T299	4
auto[FlashPartInfo1]	auto[FlashOpRead]	706	1		T6	2		T44	12		T58	3
auto[FlashPartInfo1]	auto[FlashOpProgram]	163	1		T127	32		T128	32		T146	1
auto[FlashPartInfo1]	auto[FlashOpErase]	2	1		T146	1		T442	1		-	-
auto[FlashPartInfo1]	auto[FlashOpInvalid]	2	1		T146	2		-	-		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1723	1		T5	38		T6	8		T27	1
auto[FlashPartInfo2]	auto[FlashOpProgram]	897	1		T6	6		T44	4		T29	3
auto[FlashPartInfo2]	auto[FlashOpErase]	21	1		T140	1		T126	1		T211	2
auto[FlashPartInfo2]	auto[FlashOpInvalid]	8	1		T443	4		T444	2		T445	2