Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.62	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	1	31	96.88

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	1	31	96.88	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30081	1		T3	716		T4	2		T19	4
auto[1]	37	1		T355	1		T121	1		T356	11
auto[2]	56	1		T28	1		T144	1		T78	1
auto[3]	228	1		T21	1		T27	1		T59	1

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7616	1		T3	179		T19	1		T21	1
evic_idx[1]	7597	1		T3	179		T19	1		T27	1
evic_idx[2]	7593	1		T3	179		T4	2		T19	1
evic_idx[3]	7596	1		T3	179		T19	1		T27	1

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	29495	1		T3	716		T4	2		T19	4
evic_op[2]	305	1		T21	1		T28	1		T59	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	1	31	96.88	1

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[3]]	[evic_op[2]]	[auto[1]]	0	1	1

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7315	1		T3	179		T19	1		T81	100
evic_idx[0]	evic_op[1]	auto[1]	7	1		T356	2		T357	2		T358	1
evic_idx[0]	evic_op[1]	auto[2]	6	1		T359	2		T360	4		-	-
evic_idx[0]	evic_op[1]	auto[3]	52	1		T27	1		T143	2		T140	1
evic_idx[0]	evic_op[2]	auto[0]	59	1		T152	8		T277	5		T361	1
evic_idx[0]	evic_op[2]	auto[1]	2	1		T121	1		T362	1		-	-
evic_idx[0]	evic_op[2]	auto[2]	5	1		T144	1		T201	1		T363	1
evic_idx[0]	evic_op[2]	auto[3]	19	1		T21	1		T59	1		T195	1
evic_idx[1]	evic_op[1]	auto[0]	7316	1		T3	179		T19	1		T27	1
evic_idx[1]	evic_op[1]	auto[1]	7	1		T356	3		T357	1		T358	1
evic_idx[1]	evic_op[1]	auto[2]	5	1		T359	2		T364	1		T360	2
evic_idx[1]	evic_op[1]	auto[3]	47	1		T143	2		T140	2		T211	3
evic_idx[1]	evic_op[2]	auto[0]	59	1		T152	8		T144	1		T232	1
evic_idx[1]	evic_op[2]	auto[1]	3	1		T355	1		T365	1		T366	1
evic_idx[1]	evic_op[2]	auto[2]	4	1		T196	1		T367	1		T363	1
evic_idx[1]	evic_op[2]	auto[3]	5	1		T334	1		T368	1		T369	1
evic_idx[2]	evic_op[1]	auto[0]	7318	1		T3	179		T4	2		T19	1
evic_idx[2]	evic_op[1]	auto[1]	7	1		T356	2		T357	2		T358	1
evic_idx[2]	evic_op[1]	auto[2]	3	1		T364	1		T360	2		-	-
evic_idx[2]	evic_op[1]	auto[3]	44	1		T143	2		T140	1		T211	5
evic_idx[2]	evic_op[2]	auto[0]	59	1		T152	8		T230	1		T277	5
evic_idx[2]	evic_op[2]	auto[1]	1	1		T286	1		-	-		-	-
evic_idx[2]	evic_op[2]	auto[2]	3	1		T28	1		T78	1		T367	1
evic_idx[2]	evic_op[2]	auto[3]	8	1		T370	1		T371	1		T372	1
evic_idx[3]	evic_op[1]	auto[0]	7317	1		T3	179		T19	1		T27	1
evic_idx[3]	evic_op[1]	auto[1]	10	1		T356	4		T357	2		T358	1
evic_idx[3]	evic_op[1]	auto[2]	2	1		T359	1		T360	1		-	-
evic_idx[3]	evic_op[1]	auto[3]	39	1		T143	3		T140	1		T211	2
evic_idx[3]	evic_op[2]	auto[0]	60	1		T152	8		T137	1		T277	5
evic_idx[3]	evic_op[2]	auto[2]	4	1		T367	2		T373	1		T289	1
evic_idx[3]	evic_op[2]	auto[3]	14	1		T374	1		T375	1		T376	1