Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	37011	1		T39	16689		T343	2678		T92	14654
rd_lvl[2]	60564	1		T39	12495		T344	12240		T343	2546
rd_lvl[3]	12343	1		T228	4340		T344	260		T343	1526
rd_lvl[4]	29539	1		T228	3785		T218	654		T343	1549
rd_lvl[5]	11961	1		T5	1643		T328	2010		T218	64
rd_lvl[6]	20873	1		T5	773		T280	469		T328	1689
rd_lvl[7]	16291	1		T280	1438		T328	362		T345	388
rd_lvl[8]	18886	1		T5	22		T280	1145		T125	908
rd_lvl[9]	5960	1		T125	247		T346	141		T343	1730
rd_lvl[10]	4435	1		T346	138		T343	1106		T347	1245
rd_lvl[11]	6865	1		T5	23		T204	198		T35	273
rd_lvl[12]	8670	1		T204	1368		T35	215		T36	286
rd_lvl[13]	3101	1		T38	439		T348	179		T349	49
rd_lvl[14]	5813	1		T38	1066		T35	67		T36	1
rd_lvl[15]	1263	1		T34	137		T348	10		T350	14