Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	369453	1		T1	1		T2	1		T3	1
all_pins[1]	369453	1		T1	1		T2	1		T3	1
all_pins[2]	369453	1		T1	1		T2	1		T3	1
all_pins[3]	369453	1		T1	1		T2	1		T3	1
all_pins[4]	369453	1		T1	1		T2	1		T3	1
all_pins[5]	369453	1		T1	1		T2	1		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1854974	1		T1	6		T2	6		T3	6
values[0x1]	361744	1		T5	3632		T29	1599		T38	3010
transitions[0x0=>0x1]	332424	1		T5	3547		T29	1599		T38	3010
transitions[0x1=>0x0]	332416	1		T5	3547		T29	1599		T38	3010

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	369312	1		T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	141	1		T263	6		T264	1		T336	1
all_pins[0]	transitions[0x0=>0x1]	70	1		T263	1		T337	2		T338	2
all_pins[0]	transitions[0x1=>0x0]	75	1		T263	1		T264	2		T337	2
all_pins[1]	values[0x0]	369307	1		T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	146	1		T263	6		T264	3		T336	1
all_pins[1]	transitions[0x0=>0x1]	115	1		T263	4		T264	2		T337	2
all_pins[1]	transitions[0x1=>0x0]	1233	1		T34	122		T350	2		T377	1074
all_pins[2]	values[0x0]	368189	1		T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	1264	1		T34	122		T350	2		T377	1074
all_pins[2]	transitions[0x0=>0x1]	43	1		T263	2		T264	2		T336	3
all_pins[2]	transitions[0x1=>0x0]	243923	1		T5	2461		T38	1505		T39	29184
all_pins[3]	values[0x0]	124309	1		T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	245144	1		T5	2461		T38	1505		T39	29184
all_pins[3]	transitions[0x0=>0x1]	217198	1		T5	2376		T38	1505		T39	26122
all_pins[3]	transitions[0x1=>0x0]	87041	1		T5	1086		T29	1599		T38	1505
all_pins[4]	values[0x0]	254466	1		T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	114987	1		T5	1171		T29	1599		T38	1505
all_pins[4]	transitions[0x0=>0x1]	114971	1		T5	1171		T29	1599		T38	1505
all_pins[4]	transitions[0x1=>0x0]	46	1		T263	2		T264	2		T337	1
all_pins[5]	values[0x0]	369391	1		T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	62	1		T263	2		T264	2		T337	2
all_pins[5]	transitions[0x0=>0x1]	27	1		T264	1		T338	1		T339	1
all_pins[5]	transitions[0x1=>0x0]	98	1		T263	4		T264	1		T336	1