Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	284	1		T263	7		T264	7		T336	4
all_values[1]	284	1		T263	7		T264	7		T336	4
all_values[2]	284	1		T263	7		T264	7		T336	4
all_values[3]	284	1		T263	7		T264	7		T336	4
all_values[4]	284	1		T263	7		T264	7		T336	4
all_values[5]	284	1		T263	7		T264	7		T336	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	942	1		T263	18		T264	28		T336	18
auto[1]	762	1		T263	24		T264	14		T336	6

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	550	1		T263	13		T264	11		T336	9
auto[1]	1154	1		T263	29		T264	31		T336	15

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	980	1		T263	19		T264	19		T336	18
auto[1]	724	1		T263	23		T264	23		T336	6

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	103	1		T263	1		T264	4		T336	3
all_values[0]	auto[0]	auto[1]	auto[1]	62	1		T263	1		T336	1		T337	2
all_values[0]	auto[1]	auto[0]	auto[1]	64	1		T263	2		T264	2		T338	3
all_values[0]	auto[1]	auto[1]	auto[1]	55	1		T263	3		T264	1		T337	2
all_values[1]	auto[0]	auto[0]	auto[1]	97	1		T263	1		T264	2		T336	3
all_values[1]	auto[0]	auto[1]	auto[1]	61	1		T263	1		T264	1		T336	1
all_values[1]	auto[1]	auto[0]	auto[1]	69	1		T263	2		T264	2		T337	2
all_values[1]	auto[1]	auto[1]	auto[1]	57	1		T263	3		T264	2		T337	2
all_values[2]	auto[0]	auto[0]	auto[0]	82	1		T263	2		T264	1		T337	2
all_values[2]	auto[0]	auto[1]	auto[0]	76	1		T263	3		T264	1		T336	1
all_values[2]	auto[1]	auto[0]	auto[1]	69	1		T263	1		T264	3		T338	2
all_values[2]	auto[1]	auto[1]	auto[1]	57	1		T263	1		T264	2		T336	3
all_values[3]	auto[0]	auto[0]	auto[0]	92	1		T263	2		T264	4		T336	3
all_values[3]	auto[0]	auto[1]	auto[0]	58	1		T338	3		T339	1		T340	1
all_values[3]	auto[1]	auto[0]	auto[1]	65	1		T263	1		T264	3		T336	1
all_values[3]	auto[1]	auto[1]	auto[1]	69	1		T263	4		T337	1		T338	1
all_values[4]	auto[0]	auto[0]	auto[0]	64	1		T263	2		T264	1		T336	4
all_values[4]	auto[0]	auto[0]	auto[1]	20	1		T263	1		T338	1		T341	1
all_values[4]	auto[0]	auto[1]	auto[0]	58	1		T264	2		T337	1		T338	1
all_values[4]	auto[0]	auto[1]	auto[1]	29	1		T263	1		T338	1		T342	2
all_values[4]	auto[1]	auto[0]	auto[1]	56	1		T263	3		T264	2		T337	2
all_values[4]	auto[1]	auto[1]	auto[1]	57	1		T264	2		T337	2		T338	3
all_values[5]	auto[0]	auto[0]	auto[0]	67	1		T264	2		T336	1		T337	2
all_values[5]	auto[0]	auto[0]	auto[1]	37	1		T264	1		T336	1		T337	1
all_values[5]	auto[0]	auto[1]	auto[0]	53	1		T263	4		T337	1		T338	2
all_values[5]	auto[0]	auto[1]	auto[1]	21	1		T338	2		T339	1		T342	3
all_values[5]	auto[1]	auto[0]	auto[1]	57	1		T264	1		T336	2		T337	1
all_values[5]	auto[1]	auto[1]	auto[1]	49	1		T263	3		T264	3		T337	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal